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PDF LTC2941-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC2941-1 | |
| Descripción | 1A I2C Battery Gas Gauge | |
| Fabricantes | Linear | |
| Logotipo |  |
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Features
n Indicates Accumulated Battery Charge and
Discharge
n SMBus/I2C Interface
n Integrated 50mΩ High Side Sense Resistor
n ±1A Sense Current Range
n High Accuracy Analog Integration
n 1% Charge Accuracy
n Configurable Alert Output/Charge Complete Input
n 2.7V to 5.5V Operating Range
n Quiescent Current Less than 100µA
n Small 6-Pin 2mm × 3mm DFN package
Applications
n Low Power Handheld Products
n Cellular Phones
n MP3 Player
n Cameras
n GPS
LTC2941-1
1A I2C Battery Gas Gauge
with Internal Sense Resistor
Description
The LTC®2941-1 measures battery charge state in battery-
powered handheld PC and portable product applications.
Its operating range is perfectly suited for single cell Li-Ion
batteries. A precision coulomb counter integrates current
through an internal sense resistor between the battery’s
positive terminal and the load or charger. The measured
charge is stored in internal registers. An SMBus/I2C in-
terface accesses and configures the device.
The LTC2941-1 features programmable high and low
thresholds for accumulated charge. If a threshold is ex-
ceeded, the device communicates an alert using either the
SMBus alert protocol or by setting a flag in the internal
status register.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap, ThinSOT and Bat-Track are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
CHARGER
I2C/SMBus
TO HOST
SENSE+
LTC2941-1
AL/CC
SDA
SENSE–
SCL
GND
LOAD
0.1µF
+ 1-CELL
Li-Ion
29411 TA01a
Total Charge Error vs Sense Current
1.00
VSENSE+ = 3.6V
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
1
10 100
|ISENSE| (mA)
1000
29411 TA01b
29411f
1 page  
LTC2941-1
Pin Functions
SENSE+ (Pin 1): Positive Current Sense Input and Power
Supply. Connect to the load and battery charger output.
VSENSE+ operating range is 2.7V to 5.5V.
GND (Pin 2): Device Ground. Connect directly to the nega-
tive battery terminal.
SCL (Pin 3): Serial Bus Clock Input.
SDA (Pin 4): Serial Bus Data Input and Output.
AL/CC (Pin 5): Alert Output or Charge Complete Input.
Configured either as an SMBus alert output or charge
complete input by control register bits B[2:1]. At power-up,
the pin defaults to alert mode conforming to the SMBus
alert response protocol. It behaves as an open-drain logic
output that pulls to GND when a value in the threshold
registers is exceeded.
When configured as a charge complete input, a high level
at CC sets the value of the accumulated charge (registers
C, D) to FFFFh. Coulomb counting starts when the input
returns to low level.
SENSE– (Pin 6): Negative Current Sense Input. Connect
SENSE– to the positive battery terminal. Current from/into
this pin must not exceed 1A in normal operation.
Exposed Pad (Pin 7): Do Not Connect. Soldering the
exposed pad to adequate electrically isolated copper area
is recommended for best thermal performance.
29411f
5 Page 
LTC2941-1
Applications Information
device. In addition to transmitters and receivers, devices
can also be classified as masters or slaves when perform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. At the same time any device ad-
dressed is considered a slave. The LTC2941-1 always
acts as a slave. Figure 4 shows an overview of the data
transmission on the I2C bus.
Start and Stop Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has finished com-
municating with the slave, it issues a STOP condition by
transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission. When the bus is
in use, it stays busy if a repeated START (Sr) is generated
instead of a STOP condition. The repeated START (Sr)
conditions are functionally identical to the START (S).
Data Transmission
After a START condition, the I2C bus is considered busy
and data transfer begins between a master and a slave. As
data is transferred over I2C in groups of nine bits (eight
data bits followed by an acknowledge bit), each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an acknowledge (ACK) by pulling SDA low or leaves
SDA high to indicate a not-acknowledge (NAK) condition.
Change of data state can only happen while SCL is low.
Write Protocol
The master begins communication with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 5. The LTC2941-
1 acknowledges this by pulling SDA low and then the
master sends a command byte which indicates which
internal register the master is to write. The LTC2941-1
acknowledges and then latches the command byte into its
internal register address pointer. The master delivers the
data byte, the LTC2941-1 acknowledges once more and
latches the data into the desired register. The transmission
is ended when the master sends a STOP condition. If the
master continues by sending a second data byte instead
of a stop, the LTC2941-1 acknowledges again, increments
its address pointer and latches the second data byte in the
following register, as shown in Figure 6.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 7. The LTC2941-1
acknowledges and then the master sends a command byte
which indicates which internal register the master is to
read. The LTC2941-1 acknowledges and then latches the
command byte into its internal register address pointer. The
master then sends a repeated START condition followed
by the same seven bit address with the R/W bit now set
to one. The LTC2941-1 acknowledges and sends the con-
tents of the requested register. The transmission is ended
when the master sends a STOP condition. If the master
acknowledges the transmitted data byte, the LTC2941-1
increments its address pointer and sends the contents of
the following register as shown in Figure 8.
Alert Response Protocol
In a system where several slaves share a common inter-
rupt line, the master can use the alert response address
(ARA) to determine which device initiated the interrupt
(Figure 9).
The master initiates the ARA procedure with a START con-
dition and the special 7-bit ARA bus address (0001100)
followed by the read bit (R) = 1. If the LTC2941-1 is as-
serting the AL/CC pin in alert mode, it acknowledges and
responds by sending its 7-bit bus address (1100100) and
a 1. While it is sending its address, it monitors the SDA pin
to see if another device is sending an address at the same
time using standard I2C bus arbitration. If the LTC2941-1
is sending a 1 and reads a 0 on the SDA pin on the rising
edge of SCL, it assumes another device with a lower ad-
dress is sending and the LTC2941-1 immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC2941-1 will
stop pulling down the AL/CC pin and will not respond to
further ARA requests until a new alert event occurs.
29411f
11
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| PDF Descargar | [ Datasheet LTC2941-1.PDF ] | |
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