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PDF CME8000 Data sheet ( Hoja de datos )
| Número de pieza | CME8000 | |
| Descripción | RC Receiver IC | |
| Fabricantes | C-MAX | |
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Data Sheet
CME8000
RC Receiver IC
C-MAX
The RF Technology Specialist
1 Short Description
The CME8000 is a BiCMOS integrated straight through receiver with build in very high sensitivity
and a pre-decoding of the time signal transmitted from WWVB, DCF77, JJY, MSF and HBG. The
receiver is prepared for multi-mode reception by using an integrated logic. Integrated functions as
stand by mode, integrated antenna switching, integrated crystal switching and a hold mode
function offer features for universal applications.
The power down mode increases the battery lifetime significantly and makes the device ideal for all
kinds of radio controlled time pieces.
2 Features
o Low power consumption (<100µA)
o Very high sensitivity (0.4µV)
o Build in pulse decoding for different protocols
o Switchable for 3 different frequencies
o High selectivity by using crystal filter
o Power down mode
o Only a few external components necessary
o AGC hold mode
o Wide frequency range (40 ... 120 kHz)
o Low power applications (1.2 .. 5.0 V)
o Automatic protocol recognition
o Pre-decoded protocol information
o Fast data transfer to CPU (100ms)
o Use of the CPU clock (32768Hz)
o Improved noise resistance
o Integrated AGC adaptation
Two built-in low impedance antenna switches
(40 Ohm/3V)
o True Bit strength indication
Benefits
o Extended Battery operating time
o Decoding of the signal extremely simplified
o Simplified micro controller software
o Simplified multi frequency handling
o Easy world time piece design
o Automatic country recognition
o True signal quality information
Block Diagram
QIN QLOUT QMOUT QHOUT
ANT1
cryst al switch
IN1
IN2
ANT2
AGC
GND
SPEC No.
CME8000
Revision
B.11
State
11.03.05
VCC
VL PON GNDL
Bias
rect.-
AGC
TCO
Logic
contr. unit
CLKS EL
CLOCK
I/O DR
Unit
DATA
DT
BS I1
BS I2
DEM PK
Figure 1.
SS1 SS2
HLD
C-MAX printed
14.03.2005
Version
English
Page
1 of 21
1 page  
Data Sheet CME8000
C-MAX
DEM
Demodulator output. To ensure the function, an
external capacitor has to be connected at this
output.
VCC
Pad 5
Pin 5
NOTE: Automatic adjustment of PK and DEM
timing
To realize a good regulation timings of the
demodulator and the peak detector the charge
and discharge currents for the capacitors at DEM
and PK have different values for the different
protocols. This is automatically switched internally
by choosing the protocol with SS1 and SS2.
DEM
Pad 10
Pin 12
GND
Pad 9
Pin 9
25k
Figure 7.
PK
Peak detector output. An external capacitor has to
be connected to ensure the function of the peak
detector. The value of the capacitance influences
the AGC regulation time.
VCC
Pad 5
Pin 5
VCC, GND, VL, GNDL
VCC and GND are the supply voltage inputs for the
analog part. VL and GNDL are the supply voltage
inputs for the digital part. The positive supplies
have to be connected externally, and also the
ground pins.
To power down the circuitry it is recommended to
use the PON input and not to switch the power
supply. Switching the power supply results in a
long power up waiting time.
VCC
Pad 5
Pin 5
VL
Pad 25
Pin 27
PK
Pad 12
Pin 13
2k
GND
Pad 9
Pin 9
Figure 8.
+ from
GND
- demodulator
Pad 9
Pin 9
Figure 9.
GNDL
Pad 16
Pin 18
SPEC No.
CME8000
Revision
B.11
State
11.03.05
C-MAX printed
14.03.2005
Version
English
Page
5 of 21
5 Page 
Data Sheet CME8000
C-MAX
11 Time Diagram for normal read out (only at end-of-minute)
DR
100 ms
DT
DATA
1 max. frequ. 10kHz
0 min. high or low 40µs
64 clock cycles
x 1101
Sec 0...............................................Sec 59
3 protocol bits + 1 signal bit + 60 data bits
X: can be 1 or 0 depending
on the content of the last bit
from the previous bit stream
In case after reset, X=0
Time diagram for protocol-identified read out (any time other than end-of minute)
DR
DT
DATA
15.6ms
1
0
4 clock cycles
x 110
4 bits
0
(3 ide ntified protocol bits + 1 signal bit)
X: can be 1 or 0 depending
on the content of the last bit
from the previous bit stream
In case after reset, X=0
Note: CONTROL BIT = 1 stands for data bits to be followed behind, continue clocking data_out
for 60 more data bits
= 0 stands for no data bits to be followed, no need to continue clocking data_out
Timing test condition: clock frequency = 1024Hz
max. input CLOCK frequency: 1025Hz
min. input CLOCK frequency: 1023Hz
Wake up time before DT: 1ms
SPEC No.
CME8000
Revision
B.11
State
11.03.05
C-MAX printed
14.03.2005
Version
English
Page
11 of 21
11 Page | ||
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| PDF Descargar | [ Datasheet CME8000.PDF ] | |
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