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PDF MDT10F6301 Data sheet ( Hoja de datos )
| Número de pieza | MDT10F6301 | |
| Descripción | 8-bit Micro-controller | |
| Fabricantes | Micon Design Technology | |
| Logotipo |  |
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1. General Description
This 8-bit Micro-controller uses a fully static
CMOS technology to achieve high speed, small
size, low power and high noise immunity.
On chip memory includes 2 K words of Flash
ROM, and 128 bytes of EEPROM, and 96 bytes
of static RAM.
2. Features
Fully CMOS static design
8-bit data bus
On chip flash ROM size :
MDT10F6301 -- 2 K words
Internal RAM size :
MDT10F6301 -- 96 bytes
(96 general purpose registers)
128 bytes of EEPROM
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.3V ~ 5.5 V
Watchdog timer with on-chip RC oscillator
Interrupt capability
Timer0 : 8-bit timer with 3-bit prescaler
Timer1 : 16-bit timer with 2-bit prescaler
One analog comparator module
Sleep mode for power saving
PA with port change wake-up interrupt
Power-on Reset
14 I/O pins with their own independent
direction control
3. Applications
The application areas of this MDT10F6301 range
from appliance motor control and high speed
MDT10F6301
automotive to low power remote
transmitters/receivers, pointing devices, and
telecommunications processors, such as Remote
controller, small instruments, chargers, toy,
automobile and PC peripheral … etc.
4. Pin Assignment
MDT10F6301P11 (DIP)
MDT10F6301S11 (SOP)
PC6
Vdd
OSC1/PA5
OSC2/PA4
PA3
PC5
PC4
PC3
1
2
3
4
5
6
7
8
16 PC7
15 Vss
14 PA0/CIN+
13 PA1/CIN-
12 PA2/INT
11 PC0
10 PC1
9 PC2
MDT10F6301P13 (DIP)
MDT10F6301S13 (SOP)
PC6
Vdd
OSC1/PA5
OSC2/PA4
/MCLR
PC5
PC4
PC3
1
2
3
4
5
6
7
8
16 PC7
15 Vss
14 PA0/CIN+
13 PA1/CIN-
12 PA2/INT
11 PC0
10 PC1
9 PC2
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.1
2008/4 Ver. 1.0
1 page  
MDT10F6301
(1). 00H or 80H : IAR ( Indirect Address Register)
Use contents of MSR to address data memory (not a physical register)
(2). 01H : RTCC (Timer0 Counter)
8-bit real time clock/counter
(3). 02H or 82H : PCL (Program Counter Low Byte)
Low order 8 bits of the Program Counter (PC)
(4). 03H or 83H : STATUS (Status register)
Bit
0
1
2
3
4
5
6—7
Symbol
C
HC
Z
/PF
/TF
page
——
Function
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
WDT time-out Flag bit
Register page select bit :
0 : 00H --- 7FH
1 : 80H --- FFH
General purpose bit
(5). 04H or 84H : MSR (Memory Select Register)
Memory Bank Select Register :
0 : 00~7F (Bank0)
1 : 80~FF (Bank1)
MSR
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(6). 05H : Port A data output register
Indirect Addressing Mode
Port A
Bit 7
-
Bit 6
-
Bit 5
PA5
Bit 7-6 : Unimplemented
Bit 5-0 : PA5~PA0, I/O Register
(7). 06H : Unimplemented Register.
Bit 4
PA4
Bit 3
PA3
Bit 2
PA2
Bit 1
PA1
Bit 0
PA0
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.5
2008/4 Ver. 1.0
5 Page 
Bit 7 : Comparator Voltage Reference Enable Bit
0 = Comparator voltage reference disable
1 = Comparator voltage reference enable
MDT10F6301
Bit 5 : Comparator Voltage Reference Range Select Bit
0 = High range ; CVref = Vdd/4 + (CVR3:CVR0/32)*Vdd
1 = Low range ; CVref = (CVR3:CVR0/24)*Vdd
Bit 3-0 : Comparator Voltage Reference Value Selection
When CVRRS = 0, CVref = Vdd/4 + (CVR3:CVR0/32)*Vdd
When CVRRS = 1, CVref = (CVR3:CVR0/24)*Vdd
(35). 9AH : EEPROM data register.
Bit 7
Bit 6
EEDATA EED7
EED6
Bit 5
EED5
Bit 4
EED4
Bit 3
EED3
Bit 2
EED2
Bit 1
EED1
Bit 0
EED0
(36). 9BH : EEPROM address register.
Bit 7
Bit 6 Bit 5
EEADR - EEAD6 EEAD5
Bit 4
EEAD4
Bit 3
EEAD3
Bit 2
EEAD2
Bit 1
EEAD1
Bit 0
EEAD0
(37). 9CH : EEPROM control register 1.
Bit 7
Bit 6 Bit 5
EECON1
-
-
-
Bit 4
-
Bit 3
Bit 2
WRERR WREN
Bit 1
WR
Bit 0
RD
Bit 7~4 is unimplemented : Read as “0”
WRERR : EEPROM Write Error Flag Bit.
0 = The EEPROM write operation completed
1 = The EEPROM write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
WREN : EEPROM Write Enable Bit.
0 = Inhibits write to the data EEPROM
1 = Allows write cycles
WR : Write Control Bit.
0 = Write cycle to the data EEPROM is complete
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete.
The WR bit can only be set (not clear) in software.)
RD : Read Control Bit.
0 = Does not initiate an EEPROM read.
1 = Initiates an EEPROM read (read takes once cycle. RD is cleared in hardware.
The RD bit can only be set (not clear) in software.)
(38). 9DH : EEPROM control register 2.
Bit 7
Bit 6 Bit 5
EECON2
-
-
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Write only ; Read as “0”
When write data to the EEPROM must write 55/H to EECON2,
and writ AA/H to EECON2 then set WR bit; the EEPROM can write data inside for write each byte.
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.11
2008/4 Ver. 1.0
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MDT10F6301.PDF ] | |
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