|
|
PDF PS20100 Data sheet ( Hoja de datos )
| Número de pieza | PS20100 | |
| Descripción | Wideband PLL FM Demodulator | |
| Fabricantes | Plessey Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PS20100 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
PS20100
Wideband PLL FM Demodulator
Preliminary Information
FEATURES
• Single chip PLL system for wideband FM
demodulation
• Simple low component count application
• Allows for application of threshold extension
• Fully balanced low radiation design
• High operating input sensitivity
• Improved VCO stability with variations in supply or
temperature
• AGC detect and bias adjust
• 75Ω video output drive with low distortion levels
• Dynamic self biasing analog AFC
• Full ESD Protection (Normal ESD handling procedures should
be observed)
APPLICATIONS
• Satellite receiver systems
• Data communications Systems
Data Sheet 210893 issue 1 Nov-10
Ordering Information
PS20100/KG/MPAS
Package 16 lead SOIC (0.150” body width)
-20°C to +80°C
The PS20100 is a wideband PLL FM
demodulator, intended for application in
satellite tuners and data communication
systems.
The device contains all elements
necessary, with the exception of an external
oscillator sustaining network and loop
feedback components, to form a complete
PLL system operating at frequencies up to
800MHz.
An AFC with window adjust is provided,
whose output signal can be used to correct
for any frequency drift at the head end local
oscillator.
Fig. 1 Pin Connections – Top View
Data Sheet 210893
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
1
http://www.Datasheet4U.com
1 page  
PS20100
FUNCTIONAL DESCRIPTION
The PS20100 is a wideband PLL FM demodulator, optimised for application in satellite receiver systems and
requiring a minimum external component count. It contains all the elements required for construction of a phase locked
loop circuit, with the exception of tuning components for the local oscillator, and an AFC detector circuit for generation of
error signal to correct for any frequency drift in the outdoor unit local oscillator.
A block diagram is contained in Figure 2 and the typical application in Figure 4.
The internal pin connections are contained in Figures 7 and 7a
In normal applications the second satellite IF frequency of typically 402 or 479.5MHz is fed to the RF preamplifier,
which has a working sensitivity of typically -40 dBm, depending on application and layout. The preamplifier
contains an RF level detect circuit, which generates an AGC signal that can be used for controlling the gain of the IF
amplifier stages, so maintaining a fixed level to the RF input of the PS20100, for optimum threshold performance.
The bias point of the AGC circuit can be adjusted to cater for variation in AGC line voltage requirement and device
input power. The typical AGC curves are shown in Fig. 10. It is recommended that the device is operated with an input
signal between -30 and -35dBm. This ensures optimum linearity threshold performance, and gives a good safety margin
over the typical sensitivity of -40dBm.
The output of the preamplifier is fed to the mixer section which is of balanced design for low radiation. In this stage the RF
signal is mixed with the local oscillator frequency, which is generated by an on–board oscillator. The oscillator block
uses an external varactor tuned sustaining network and is optimised for high linearity over the normal deviation
range. A typical frequency versus voltage characteristic for the oscillator is contained in Figure 8. The loop output is
designed to compensate for first order temperature variation effects; the typical stability is shown in Figure 9.
The output of the mixer is then fed to the loop amplifier around which feedback is applied to determine loop transfer
characteristic. Feedback can be applied either in differential or single ended mode; if the appropriate phase detector
gains are assumed in calculating loop filters, both modes should give the same loop response.
The loop amplifier drives a 75Ω output impedance buffer amplifier, which can either be connected to a 75Ω load or
used to drive a high input impedance stage giving greater linearity and approximately 6dB higher demodulated signal
output level.
DESIGN OF PLL LOOP PARAMETERS
Fig. 5 PLL Loop
Data Sheet 210893
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
5
5 Page 
PS20100
Fig.11 Layout of demo board with component locations
For further information about this and other products, please visit:
www.plesseysemiconductors.com
Legal Notice
Product information provided by Plessey Semiconductors Limited (“Plessey”) in this document is believed to be correct and accurate. Plessey
reserves the right to change/correct the specifications and other data or information relating to products without notice but Plessey accepts no
liability for errors that may appear in this document, howsoever occurring, or liability arising from the use or application of any information or
data provided herein. Neither the supply of such information, nor the purchase or use of products conveys any licence or permission under
patent, copyright, trademark or other intellectual property right of Plessey or third parties.
Products sold by Plessey are subject to its standard Terms and Conditions of Sale that are available on request. No warranty is given that
products do not infringe the intellectual property rights of third parties, and furthermore, the use of products in certain ways or in combination
with Plessey, or non-Plessey furnished equipments/components may infringe intellectual property rights of Plessey.
The purpose of this document is to provide information only and it may not be used, applied or reproduced (in whole or in part) for any purpose
nor be taken as a representation relating to the products in question. No warranty or guarantee express or implied is made concerning the
capability, performance or suitability of any product, and information concerning possible applications or methods of use is provided for
guidance only and not as a recommendation. The user is solely responsible for determining the performance and suitability of the product in any
application and checking that any specification or data it seeks to rely on has not been superseded.
Products are intended for normal commercial applications. For applications requiring unusual environmental requirements, extended
temperature range, or high reliability capability (e.g. military, or medical applications), special processing/testing/conditions of sale may be
available on application to Plessey.
Data Sheet 210893
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet PS20100.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PS2010 | PLASTIC SILICON RECTIFIER(VOLTAGE 50 to 1000 Volts CURRENT - 2.0 Amperes) |  Pan Jit International |
| PS20100 | Wideband PLL FM Demodulator | Plessey Semiconductors |
| PS2010R | FAST SWITCHING PLASTIC RECTIFIER(VOLTAGE - 50 to 1000 Volts CURRENT - 2.0 Amperes) | Pan Jit International |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |