|
|
PDF PT7C4307 Data sheet ( Hoja de datos )
| Número de pieza | PT7C4307 | |
| Descripción | Real-time Clock Module | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PT7C4307 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
PT7C4307
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Real-time Clock Module (I2C Bus)
Features
Using external 32.768kHz quartz crystal
Supports I2C-Bus's high speed mode (400 kHz)
Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
Programmable square wave output signal
56-byte, battery-backed, nonvolatile (NV) RAM for
data storage
Automatic power-fail detect and switch circuitry of
battery backup
Consumes less than 500nA in battery backup mode
with oscillator running
Description
The PT7C4307 serial real-time clock is a low-power
clock/calendar with a programmable square-wave output
and 56 bytes of nonvolatile RAM.
Address and data are transferred serially via a 2-wire,
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in either the
24-hour or 12-hour format with AM/PM indicator.
The PT7C4307 has a built-in power sense circuit that
detects power failures and automatically switches to the
battery supply.
Table 1 shows the basic functions of PT7C4307. More
details are shown in section: overview of functions.
Table 1. Basic functions of PT7C4307
Item
Function
Source: Crystal: 32.768kHz
1 Oscillator
Oscillator enable/disable
Oscillator fail detect
Time display
2 Time
12-hour
24-hour
Century bit
3 Alarm interrupt
4 Programmable square wave output (Hz)
5 RAM
6 Battery backup
PT7C4307
-
-
-
1, 4.096k, 8.192k, 32.768k
568
2013-06-0002
PT0206-5 06/18/13
1
1 page  
PT7C4307
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Over the operating range
Symbol
Item
fSCL SCL clock frequency
tSU;STA
START condition set-up time
tHD;STA
START condition hold time
tSU;DAT
tHD;DAT1
Data set-up time (RTC read/write)
Data hold time (RTC write)
tHD;DAT2
Data hold time (RTC read)
tSU;STO
STOP condition setup time
tBUF Bus idle time between a START and STOP condition
tLOW When SCL = "L"
tHIGH
When SCL = "H"
tr Rise time for SCL and SDA
tf Fall time for SCL and SDA
tSP* Allowable spike time on bus
CB Capacitance load for each bus line
* Note: only reference for design
Min.
-
0.6
0.6
200
35
0
0.6
1.3
1.3
0.6
-
-
-
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
-
-
-
-
-
-
-
-
0.3
0.3
50
400
Unit
kHz
s
s
ns
ns
s
s
s
s
s
s
s
ns
pF
S
SCL
SDA
tHD;STA
tLOW
fSCL
tSU;DAT
tHIGH
tHD;DAT
S Start condition
Sr Restart condition
P Stop condition
Sr
tHD;STA
tSU;STA
P tSU;STA
tSP
tBUF
tSU;STO
tHD;STA
2013-06-0002
PT0206-5 06/18/13
5
5 Page 
PT7C4307
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Starting and Stopping I2C Bus Communications
Fig 2. Starting and stopping on I2C bus
1) START condition, repeated START condition, and STOP condition
a) START condition
SDA level changes from high to low while SCL is at high level
b) STOP condition
SDA level changes from low to high while SCL is at high level
c) Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Data Transfers and Acknowledge Responses during I2C-BUS Communication
a) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
2013-06-0002
PT0206-5 06/18/13
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet PT7C4307.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PT7C4300 | Real-time Clock Module | Pericom Semiconductor |
| PT7C4302 | Real-time Clock Module | Pericom Semiconductor |
| PT7C4307 | Real-time Clock Module | Pericom Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |