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PDF CY7C68024 Data sheet ( Hoja de datos )
| Número de pieza | CY7C68024 | |
| Descripción | EZ-USB NX2LP USB 2.0 NAND Flash Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C68023/CY7C68024
EZ-USB NX2LP™ USB 2.0 NAND Flash Controller
1.0 Features
• High (480-Mbps) or full (12-Mbps) speed USB support
• Both common NAND page sizes supported
— 512bytes –Up to 1Gbit Capacity
— 2K bytes –Up to 8Gbit Capacity
• 8 chip enable pins
— Up to 8 NAND Flash single-device chips
— Up to 4 NAND Flash dual-device chips
• Industry standard ECC NAND Flash correction
— 1-bit per 256 correction
— 2-bit error detection
• Industry standard (SmartMedia) page management for
wear leveling algorithm, bad block handling, and Physical
to Logical management.
• Supports 8-bit NAND Flash interfaces
• Supports 30ns, 50ns, 100ns NAND Flash timing
• Complies with USB Mass Storage Class Specification rev
1.0
• CY7C68024 complies with USB 2.0 Specification for Bus-
Powered Devices (TID# 40460274)
• 43-mA Typical Active Current
• Space-saving and lead-free 56-QFN package (8mm ×
8mm)
• Support for board-level manufacturing test via USB
interface
• 3.3V NAND Flash operation
• NAND Flash power management support
2.0 Introduction
™The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND
Flash controller. This controller adheres to the Mass Storage
Class Bulk-Only Transport Specification. The USB port of the
NX2LP is connected to a host computer directly or via the
downstream port of a USB hub. Host software issues
commands and data to the NX2LP and receives status and
data from the NX2LP using standard USB protocol.
The NX2LP supports industry leading 8-bit NAND Flash inter-
faces and both common NAND page sizes of 512 and 2k
bytes. Eight chip enable pins allow the NX2LP to be connected
to up to eight single- or four dual-device NAND Flash chips.
Certain NX2LP features are configurable, enabling the NX2LP
to meet the needs of different designs’ requirements.
24 MHz
Xtal
Chip Reset
PLL
VBUS
D+
D-
USB 2.0
Xceiver
EZ-USB NX2LP
Internal Control Logic
Control
Write Protect
LED2#
LED1#
NAND Control Signals
NAND Flash
Interface
Logic
Chip Enable Signals
Smart HS/
FS USB
Engine
Data
Figure 1-1. NX2LP Block Diagram
8-bit Data Bus
Cypress Semiconductor Corporation
Document #: 38-08055 Rev. *A
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised March 16, 2005
1 page  
CY7C680w2w3w/.CDaYta7ShCee6t48U0.co2m4
4.0 Applications
The NX2LP is a high-speed USB 2.0 peripheral device that
connects NAND Flash devices to a USB host using the USB
Mass Storage Class protocol.
4.1 Additional Resources
• CY3685 EZ-USB NX2LP Development Kit
• CY4618 EZ-USB NX2LP Reference Design Kit
• USB Specification version 2.0
• USB Mass Storage Class Bulk Only Transport Specification,
http://www.usb.org/developers/data/devclass/
usbmassbulk_10.pdf.
internal ROM. This mode allows for first-time programming of
the configuration data memory area, as well as board-level
manufacturing tests.
A unique USB serial number is required for each device in
order to comply with the USB Mass Storage specification.
Also, Cypress requires designers to use their own Vendor ID
for final products. The Vendor ID is obtained through regis-
tration with the USB Implementor’s Forum (USB-IF), and the
Product ID is determined by the designer.
Cypress provides all the software tools and drivers necessary
for properly programming and testing the NX2LP. Please refer
to the documentation in the development or reference design
kit for more information on these topics.
5.0 Functional Overview
5.1 USB Signaling Speed
The NX2LP operates at two of the three rates defined in the
USB Specification Revision 2.0 dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbits/sec
• High speed, with a signaling bit rate of 480 Mbits/sec.
The NX2LP does not support the low-speed signaling rate of
1.5 Mbits/sec.
Start-up
Yes NAND Flash
Present?
No
5.2 NAND Flash Interface
During normal operation the NX2LP supports an 8-bit I/O
interface, eight chip enable pins, and other control signals
compatible with industry standard NAND Flash devices.
6.0 Enumeration
NAND Flash
Programmed?
No
During the start-up sequence, internal logic checks for the
presence of NAND Flash with valid configuration data in the
configuration data memory area. If valid configuration data is
found, the NX2LP uses the values stored in NAND Flash to
configure the USB descriptors for normal operation as a USB
mass storage device. If no NAND Flash is detected, or if no
valid configuration data is found in the configuration data
memory area, the NX2LP uses the default values from internal
ROM space for manufacturing mode operation. The two
modes of operation are described in sections 6.1 and 6.2
below.
Yes
Load Custom
Descriptors and
Configuration Data
Load Default
Descriptors and
Configuration Data
6.1 Normal Operation Mode
In Normal Operation Mode, the NX2LP behaves as a USB 2.0
Mass Storage Class NAND Flash controller. This includes all
typical USB device states (powered, configured, etc.). The
USB descriptors are returned according to the data stored in
the configuration data memory area. Normal read and write
access to the NAND Flash is available in this mode.
6.2 Manufacturing Mode
In Manufacturing mode, the NX2LP enumerates using the
default descriptors and configuration data that are stored in
Enumerate As
USB Mass
Storage Device
Enumerate As
Generic NX2LP
Device
Normal Operation
Mode
Manufacturing
Mode
Figure 6-1. NX2LP Enumeration Process
Document #: 38-08055 Rev. *A
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY7C68024.PDF ] | |
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