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PDF LTC1741 Data sheet ( Hoja de datos )
| Número de pieza | LTC1741 | |
| Descripción | 12-Bit 65Msps Low Noise ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Sample Rate: 65Msps
s 72dB SNR and 85dB SFDR (3.2V Range)
s 70.5dB SNR and 87dB SFDR (2V Range)
s No Missing Codes
s Single 5V Supply
s Power Dissipation: 1.275W
s Selectable Input Ranges: ±1V or ±1.6V
s 240MHz Full Power Bandwidth S/H
s Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745(12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743(12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741(12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747(12-Bit)
s 48-Pin TSSOP PaUckage
APPLICATIO S
s Telecommunications
s Receivers
s Cellular Base Stations
s Spectrum Analysis
s Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1741www.DataSheet4U.com
12-Bit, 65Msps Low Noise ADC
DESCRIPTIO
The LTC®1741 is an 65Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of ±1V
and ±1.6V along with a resistor programmable mode
allow the LTC1741’s input range to be optimized for a wide
variety of applications.
The LTC1741 is perfect for demanding communications
applications with AC performance that includes 72dB
SNR and 85dB spurious free dynamic range. Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies of up
to 70MHz with excellent noise performance. DC specs
include ±1 LSB INL and ±0.8LSB DNL over temperature.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
BLOCK DIAGRA
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT AIN–
SENSE
RANGE
SELECT
VCM
4.7µF
2.35VREF
65Msps, 12-Bit ADC with a ±1V Differential Input Range
S/H
12-BIT
CORRECTION
LOGIC AND
12
OUTPUT
AMP
PIPELINED ADC
SHIFT
LATCHES
REGISTER
OVDD
0.1µF
OF
•••
D11
D0
CLKOUT
OGND
0.5V
TO 5V
0.1µF
BUFFER
DIFF AMP
CONTROL LOGIC
VDD
1µF
5V
1µF
1µF
GND
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA REFHB ENC ENC MSBINV
0.1µF DIFFERENTIAL
1µF ENCODE INPUT
1741 BD
OE
1741f
1
1 page  
LTC1741www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND
(unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When this pin voltage is taken below GND or above 0VDD, it will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND or above 0VDD without latchup.
Note 5: VDD = 5V, fSAMPLE = 65MHz, differential ENC/ENC = 2VP-P 65MHz
sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
INL, 3.2V Range
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
1741 G01
Averaged 8192 Point FFT,
Input Frequency = 5MHz, –10dB,
3.2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
1741 G01
DNL, 3.2V Range
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
1741 G02
Averaged 8192 Point FFT,
Input Frequency = 5MHz, – 20dB,
3.2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
1741 G01
Averaged 8192 Point FFT,
Input Frequency = 5MHz, –1dB,
3.2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
1741 G03
Averaged 8192 Point FFT,
Input Frequency = 20MHz, –1dB,
3.2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
1741 G01
1741f
5
5 Page 
LTC1741www.DataSheet4U.com
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
The LTC1741 is a CMOS pipelined multistep converter.
The converter has four pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later,
see the Timing Diagram section. The analog input is
differential for improved common mode noise immunity
and to maximize the input range. Additionally, the differen-
tial input drive will reduce even order harmonics of the
sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
The LTC1741 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC1741
CMOS differential sample-and-hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(CSAMPLE) through CMOS transmission gates. This direct
capacitor sampling results in lowest possible noise for a
given sampling capacitor size. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sam-
pling capacitors and they charge to, and track the differen-
tial input voltage. When ENC/ENC transitions from low to
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
LTC1741 VDD
AIN+
CPARASITIC
4pF
VDD
AIN–
CPARASITIC
4pF
5V
CSAMPLE
4pF
CSAMPLE
4pF
2V
6k
ENC
ENC
6k
2V
BIAS
Figure 2. Equivalent Input Circuit
1741 F02
1741f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1741.PDF ] | |
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