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PDF PHB110NQ08LT Data sheet ( Hoja de datos )
| Número de pieza | PHB110NQ08LT | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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PHP/PHB110NQ08LT
N-channel TrenchMOS™ logic level FET
Rev. 01 — 29 March 2004
Product data
1. Product profile
1.1 Description
Logic level N-channel enhancement mode field-effect transistor in a plastic package
using TrenchMOS™ technology.
1.2 Features
s Logic level threshold
s Very low on-state resistance.
1.3 Applications
s Motors, lamps, solenoids
s DC-to-DC converters
s Uninterruptible power supplies
s General industrial applications.
1.4 Quick reference data
s VDS ≤ 75 V
s Ptot ≤ 230 W
s ID ≤ 75 A
s RDSon ≤ 8.5 mΩ.
2. Pinning information
Table 1: Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outline and symbol
Pin Description
Simplified outline
Symbol
1 gate (g)
2 drain (d)
[1]
mb
mb
3 source (s)
mb mounting base;
connected to
drain (d)
g
MBB076
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
d
s
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Philips Semiconductors
PHP/PHB110NQ08LT
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
VGS(th) gate-source threshold voltage
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
IDSS drain-source leakage current
IGSS gate-source leakage current
VDS = 75 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±10 V; VDS = 0 V
RDSon drain-source on-state resistance
VGS = 10 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 5 V; ID = 25 A; Figure 7 and 8
VGS = 4.5 V; ID = 25 A; Figure 8
Dynamic characteristics
Qg(tot)
Qgs
total gate charge
gate-source charge
ID = 25 A; VDD = 60 V; VGS = 10 V;
Figure 13
Qgd gate-drain (Miller) charge
Ciss
Coss
Crss
td(on)
tr
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 11
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
td(off)
turn-off delay time
tf fall time
Source-drain diode
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr reverse recovery time
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V
Qr recovered charge
Min Typ Max Unit
75 - - V
70 - - V
1 1.5 2 V
0.5 - - V
- - 2.2 V
- - 10 µA
- - 500 µA
- 2 100 nA
- 7.2 8.5 mΩ
- 15.1 17.9 mΩ
-
7.6 9
mΩ
- - 9.95 mΩ
- 127.3 - nC
- 12.5 - nC
- 54.5 - nC
- 6631 - pF
- 905 - pF
- 610 - pF
- 47 - ns
- 185 - ns
- 424 - ns
- 226 - ns
- 0.77 1.2 V
- 70 - ns
- 213 - nC
9397 750 12924
Product data
Rev. 01 — 29 March 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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8. Revision history
Table 6: Revision history
Rev Date
CPCN
Description
01 20040329 -
Product data (9397 750 12924)
PHP/PHB110NQ08LT
N-channel TrenchMOS™ logic level FET
9397 750 12924
Product data
Rev. 01 — 29 March 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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