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PDF ISL54500 Data sheet ( Hoja de datos )
| Número de pieza | ISL54500 | |
| Descripción | Single SPDT Analog Switch | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
+1.8V to +5.5V, 5Ω, Single SPDT Analog
Switch
The Intersil ISL54500 device is a low ON-resistance, low
voltage, bidirectional, single pole/double throw (SPDT)
analog switch designed to operate from a single +1.8V to
+5.5V supply. Targeted applications include battery powered
equipment that benefit from low ON-resistance and fast
switching speeds (tON = 22ns, tOFF = 15ns). The digital logic
input is 1.8V CMOS compatible when using a single +3V
supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54500 is offered in the 6 Ld 1.2mmx1.0mmx0.4mm pitch
µTDFN package, alleviating board space limitations.
The ISL54500 is a committed SPDT that consist of one
normally open (NO) and one normally closed (NC) switch.
This configuration can also be used as a 2-to-1 multiplexer.
TABLE 1. FEATURES AT A GLANCE
ISL54500
Number of Switches
1
SW
1.8V rON
1.8V tON/tOFF
3V rON
3V tON/tOFF
5V rON
5V tON/tOFF
Package
SPDT or 2-1 MUX
12Ω
70ns/52ns
6.0Ω
30ns/20ns
5.0Ω
22ns/15ns
6 Ld μTDFN
August 29, 2007
ISL54500
FN6549.1
Features
• ON-resistance (rON)
- VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0Ω
- VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0Ω
- VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ω
• rON matching between channels . . . . . . . . . . . . . . . . . 46mΩ
• rON flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . . 1.1Ω
• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V Supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
• Guaranteed break-before-make
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• 1.8V, CMOS logic compatible (+3V supply)
• Available in 6 Ld µTDFN package
• Pb-free available (RoHS compliant)
Applications
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL54500
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 5),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 6, 7) TYP (Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full 0
- V+ V
ON-Resistance, rON
V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+, 25 - 11.9 12.8 Ω
(Note 9, See Figure 5)
Full -
- 13.8 Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF (See Figure 1, Note 9)
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF (See Figure 1, Note 9)
25 - 70 - ns
Full - 130 - ns
25 - 52 - ns
Full - 100 - ns
Break-Before-Make Time Delay, tD V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, Full - 42 - ns
CL = 35pF (See Figure 3, Note 9)
Charge Injection, Q
VG = 0, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
5.8
- pC
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full -
- 0.4 V
Input Voltage High, VINH
Full 1 - - V
NOTES:
5. VIN = input voltage to perform proper function.
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
9. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
LOGIC
INPUT
V+
0V
SWITCH
INPUT
VNO
SWITCH
OUTPUT 0V
50%
tOFF
VOUT
90%
tON
tr < 20ns
tf < 20ns
90%
V+
C
SWITCH
INPUT
LOGIC
INPUT
NO or NC
IN
GND
COM
VOUT
RL CL
50Ω 35pF
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
VOUT
=
V(NO or NC)
-----------R-----L------------
RL + r(ON)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
5 FN6549.1
August 29, 2007
5 Page 
ISL54500
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E AB
PIN 1
REFERENCE
2X 0.10 C
2X 0.10 C
TOP VIEW
D
0.10 C
7X 0.08 C
DETAIL A
A
A1 A3
SIDE VIEW
C
SEATING
PLANE
DETAIL B
1
L1
4X
e
5X
3L
64
BOTTOM VIEW
b 6X
0.10 C A B
0.05 C NOTE 3
0.1x45°
CHAMFER
A1 A3
DETAIL A
DETAIL B PIN 1 LEAD
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN NOMINAL MAX
NOTES
A
0.45 0.50 0.55
-
A1 - - 0.05 -
A3 0.127 REF -
b
0.15 0.20 0.25
5
D
0.95 1.00 1.05
-
E
1.15 1.20 1.25
-
e
0.40 BSC
-
L
0.30 0.35 0.40
-
L1 0.40 0.45 0.50 -
N 62
Ne 3 3
θ 0 - 12 4
NOTES:
Rev. 2 8/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.45
0.30
0.35
0.20
0.40
LAND PATTERN 10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6549.1
August 29, 2007
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL54500.PDF ] | |
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