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PDF ATTINY22L Data sheet ( Hoja de datos )
| Número de pieza | ATTINY22L | |
| Descripción | 8-bit Microcontroller with 2K Bytes of In-System Programmable Flash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Utilizes the AVR® RISC Architecture
• AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 1MIPS Throughput at 1MHz
• Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of internal SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
• Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– On-chip RC Oscillator
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 3V, 25°C
– Active: 1.5 mA
– Idle Mode: 100 µA
– Power Down Mode: <1 µA
• I/O and Packages
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– 5 Programmable I/O Lines
– 8-pin PDIP and SOIC
• Operating Voltages
– 2.7 - 6.0V
• Speed Grade
– Internal Oscillator ~1MHz @ 5.0V
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
ATtiny22L
Preliminary
DataShee
Description
The ATtiny22L is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny22L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
Pin Configuration
PDIP/SOIC
RESET
PB3
PB4
GND
1
2
3
4
8 VCC
7 PB2 (SCK/T0)
6 PB1 (MISO/INT0)
5 PB0 (MOSI)
Rev. 1273BS–02/00
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Note: This is a summary document. For the complete 56-page
document, please visit our web site at www.atmel.com or e-mail a1t
[email protected] and request literature #1273B.
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1 page  
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Figure 3. Memory Maps
ATtiny22L
EEPROM Data Memory
$000
EEPROM
(128 x 8)
$07F
et4U.com
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DataShee
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
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North America:
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International:
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e-mail
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BBS
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© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
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Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1273BS–02/00/xM
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| PDF Descargar | [ Datasheet ATTINY22L.PDF ] | |
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