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PDF CY7C109 Data sheet ( Hoja de datos )
| Número de pieza | CY7C109 | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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009
CY7C109
CY7C1009
128K x 8 Static RAM
Features
• High speed
— tAA = 10 ns
• Low active power
— 1017 mW (max., 12 ns)
• Low CMOS standby power
— 55 mW (max.), 4 mW (Low power version)
• 2.0V Data Retention (Low power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW chip enable (CE1), an
active HIGH chip enable (CE2), an active LOW output enable
(OE), and three-state drivers. Writing to the device is accom-
plished by taking chip enable one (CE1) and write enable (WE)
inputs LOW and chip enable two (CE2) input HIGH. Data on
the eight I/O pins (I/O0 through I/O7) is then written into the
location specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
512 x 256 x 8
ARRAY
A7
A8
CE1
CE2
COLUMN
DECODER
POWER
DOWN
WE
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
Shaded areas contain preliminary information.
7C109-10
7C1009-10
10
195
10
2
I/O0
I/O1
I/O2
I/O3
A11
A9
A8
I/O4 A13
WE
CE2
I/O5 A15
VCC
NC
I/O6 A16
A14
A12
I/O7 A7
A6
109–1
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C109-12
7C1009-12
12
185
10
2
7C109-15
7C1009-15
15
155
10
2
Pin Configurations
SOJ
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3 109–2
TSOP I
Top View
(not to scale)
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
109–3
7C109-20
7C1009-20
20
140
10
—
7C109-25
7C1009-25
25
135
10
—
7C109-35
7C1009-35
35
125
10
—
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05032 Rev. **
Revised August 24, 2001
1 page  
CY7C109
CY7C1009
Switching Characteristics[3, 5] Over the Operating Range
Parameter
Description
READ CYCLE
tRC
tAA
tOHA
tACE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7]
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
tPD CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
7C109-20
7C1009-20
Min. Max.
20
20
3
20
8
0
8
3
8
0
20
20
15
15
0
0
12
10
0
3
8
7C109-25
7C1009-25
Min. Max.
25
25
5
25
10
0
10
5
10
0
25
25
20
20
0
0
15
15
0
5
10
7C109-35
7C1009-35
Min. Min.
35
35
5
35
15
0
15
5
15
0
35
35
25
25
0
0
20
20
0
5
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
Description
VDR VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention Time
tR Operation Recovery Time
Shaded areas contain preliminary information.
Conditions
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Min. Max Unit
2.0 V
50 µA
0 ns
tRC ns
Document #: 38-05032 Rev. **
Page 5 of 12
5 Page 
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
CY7C109
CY7C1009
51-85056-B
Document #: 38-05032 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY7C109.PDF ] | |
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