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PDF MTP10N10E Data sheet ( Hoja de datos )
| Número de pieza | MTP10N10E | |
| Descripción | TMOS POWER FETs 10 AMPERES 100 VOLTS RDS(on) = 0.25 OHM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP10N10E/D
™Designer's Data Sheet
TMOS IV
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced “E” series of TMOS power MOSFETs is designed
to withstand high energy in the avalanche and commutation
modes. These new energy efficient devices also offer drain–to–
source diodes with fast recovery times. Designed for low voltage,
high speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits where diode speed and commutating safe
operating area are critical, and offer additional safety margin
against unexpected voltage transients.
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode — Unclamped Inductive Switching (UIS)
Energy Capability Specified at 100°C
• Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage
Drain Current — Continuous
Drain Current — Pulsed
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
MTP10N10E
®
D
TMOS POWER FETs
10 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM
S
CASE 221A–06, Style 5
TO–220AB
Symbol
VDSS
VDGR
VGS
ID
IDM
PD
TJ, Tstg
RθJC
RθJA
TL
Value
100
100
± 20
10
25
75
0.6
– 65 to 150
Unit
Vdc
Vdc
Vdc
Adc
Watts
W/°C
°C
1.67 °C/W
62.5
275 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
1 page  
COMMUTATING SAFE OPERATING AREA (CSOA)
MTP10N10E
The Commutating Safe Operating Area (CSOA) of Figure
12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when wave-
forms similar to those of Figure 11 are present. Full or half-
bridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by de-
vice, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for-
ward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was at-
tained with dIs/dt of 400 A/µs.
30
25
20
15
dIs/dt ≤ 400 A/µs
10
5
15 V
VGS
0
90%
IS
10%
IFM dls/dt
trr
ton IRM
0.25 IRM
VDS(pk)
VDS
dVDS/dt
Vf VdsL
VR
MAX. CSOA
STRESS AREA
Figure 11. Commutating Waveforms
RGS DUT
–
VR
+
VGS
IFM
+
IS
VDS
20 V
–
Li
VR = 80% OF RATED VDS
VdsL = Vf + Li ⋅ dls/dt
Figure 13. Commutating Safe Operating Area
Test Circuit
0
0 20 40 60 80 100 120
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 12. Commutating Safe Operating Area (CSOA)
V(BR)DSS
Vds(t)
IO
L
VDS C
ID
4700 µF
250 V
VDD
t
RGS
50 Ω
Figure 14. Unclamped Inductive Switching
Test Circuit
ID(t)
VDD
+ ǒ Ǔ ǒ ǓtP
WDSR
t, (TIME)
1
2
L
IO2
V(BR)DSS
V(BR)DSS – VDD
Figure 15. Unclamped Inductive Switching
Waveforms
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MTP10N10E.PDF ] | |
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