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PDF CY7C107B Data sheet ( Hoja de datos )
| Número de pieza | CY7C107B | |
| Descripción | 1M x 1 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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07B
CY7C107B
CY7C1007B
Features
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
1M x 1 Static RAM
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the ad-
dress pins (A0 through A19).
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (DOUT)
pin.
The output pin (DOUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4 512x2048
A5 ARRAY
A6
A7
A8
COLUMN
DECODER
POWER
DOWN
DIN
DOUT
CE
WE
107B-1
Pin Configuration
SOJ
Top View
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A9
26 A8
25
24
A7
A6
23 A5
22
21
A4
NC
20 A3
19
18
A2
A1
17 A0
16 DIN
15 CE
107B-2
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
7C107B-12
7C1007B-12
12
90
2
7C107B-15
7C1007B-15
15
80
2
7C107B-20
7C1007B-20
20
75
2
7C107B-25
7C1007B-25
25
70
2
7C107B-35
7C1007B-35
35
60
2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05030 Rev. **
Revised September 7, 2001
1 page  
CY7C107B
CY7C1007B
Switching Waveforms
Read Cycle No. 1[10, 11]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
Read Cycle No. 2[11, 12]
tRC
DATA VALID
107-6
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
tACE
tLZCE
HIGH IMPEDANCE
tPU
50%
tRC
DATA VALID
Write Cycle No. 1 (CE Controlled)[13]
ADDRESS
CE
tSA
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
Notes:
9. No input may exceed VCC + 0.5V.
10. Device is continuously selected, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
tWC
tSCE
tAW
tPWE
tSD
DATA VALID
tHZCE
HIGH
IMPEDANCE
tPD
50%
ICC
ISB
107-7
tHA
tHD
107-8
Document #: 38-05030 Rev. **
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY7C107B.PDF ] | |
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