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PDF MN6152U Data sheet ( Hoja de datos )

Número de pieza MN6152U
Descripción PLL LSI with Built-In Prescaler
Fabricantes Panasonic Semiconductor 
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For Communications Equipment
MN6152U
PLL LSI with Built-In Prescaler
Overview
The MN6152U is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.8 to 2.5 V) and low power consumption (5 mW
for VDD=2.0 V, FIN=100 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: VDD=1.8 to 2.5V
Low power consumption: 5mW (VDD=2.0V,
FIN=100MHz)
High-speed operation:
FIN=175MHz
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage: 272 to
262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and refer-
ence frequency dividing stages
Pin Assignment
XIN
XOUT
FV
VDD
DOP
VSS
LD
FIN
1
2
3
4
5
6
7
8
16 OR
15 OV
14 LC
13 FR
12 PS
11 LE
10 DATA
9 CLK
(TOP VIEW)
SSOP016-P-0225

1 page




MN6152U pdf
For Communications Equipment
MN6152U
Absolute Maximum Ratings
Parameter
Power supply voltage
Input pin voltage
Output pin voltage
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VDD
VI
VO
PD
Topr
Tstg
Rating
– 0.3 to +3.5
VSS – 0.3 to VDD +0.3
VSS – 0.3 to VDD +0.3
20
–20 to +60
–55 to +125
Unit
V
mW
˚C
Operating Conditions
VSS=0V, Ta=–20 to +60˚C
Parameter
Power supply voltage
Symbol
VDD
Test Conditions
min typ max Unit
1.8 2.0 2.5 V
Electric Characteristics
VDD=2V, Ta=–20 to +60˚C
Parameter
Symbol
Test Conditions
min typ
Power supply voltage
IDD FIN=100MHz, XIN=20MHz,
PS="H"
IDstop PS ="L" (at power save operation)
Input Pins CLK, DATA, LE, and PS VDD=1.8 to 2.5V
"H" level input voltage
VIH
VDD – 0.2
"L" level input voltage
VIL
VSS
Input leakage current
ILI
Input Pin FIN VDD=1.8 to 2.5V
Input voltage
VIN
Input current
IIF
Pull-up resistor present
(PS="L")
0.4
–100
Input leakage current
Maximum operating frequency
Minimum operating frequency
ILIF
FINMAX
FINMIN
VIN=0 or 2V (PS="H")
VIN=0.4 Vp-p
VIN=0.4 Vp-p
175
Input Pin
Input voltage
Input current
XIN
VDD=1.8 to 2.5V
VIN
IIX
Pull-up resistor present
(PS="L")
0.4
2.5
Input leakage current
Maximum operating frequency
VLIX
XINMAX
VIN=0 or 2V
VIN=0.4 Vp-p
20
max Unit
2.5 mA
10 µA
VDD
V
0.2
±1.0 µA
Vp-p
µA
±20 µA
MHz
10 MHz
Vp-p
mA
5.0 µA
MHz

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