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PDF MSM7580 Data sheet ( Hoja de datos )
| Número de pieza | MSM7580 | |
| Descripción | ITU-T G.721 ADPCM TRANSCODER | |
| Fabricantes | OKI | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MSM7580 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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E2U0031-39-61
¡¡SemicondSucetormiconductor
MSM7580
ITU-T G.721 ADPCM TRANSCODER
This version: JMunS.M19795980
Previous version: Aug. 1998
GENERAL DESCRIPTION
The MSM7580 is an ADPCM transcoder which is used by the new digital cordless system. It
converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice
versa.
This device consists of two systems with full-duplex voice data channels and a data-through
mode.
The MSM7580 provides cost effective solutions for digital cordless office telephone systems
which are incorporated into PABXs and for the public base stations which are connected to the
central office through digital PSTNs.
FEATURES
• Conforms to ITU-T G.721
• Built-in Full-duplex Transcoder with Two Data channels
• PCM companding Law: A-law/µ-law selectable
• Synchronized Operation between coder and decoder, and between two channels.
• Serial PCM Data Transmission Speed: 64 kbps to 2048 kbps
• Serial ADPCM Data Transmission Speed: 32 kbps to 2048 kbps
• Hardware Reset – ITU-T G.721 Optional Reset – for each channel
• Power Down Control for each channel
• Decoder (ADPCM Æ PCM ) MUTE Mode and PAD Mode for each channel
• ADPCM Data-through Mode
• Capable of time slot conversion
• Special ADPCM Input Data Code (”0000”) Detector for each channel
• Master Clock Signal : Not necessary
• Power supply voltage/Consumption current :
+5 V ±10%, 2.5 mA/channel
• Package :
28-pin plastic SOP (SOP28-P-430-1.27-K) (Product name : MSM7580GS-K)
1/17
1 page  
¡ Semiconductor
MSM7580
SYNCP1, SYNCP2
Synchronous signal input.
SYNCP1 and SYNCP2 control the PCM data input/output timing for Channel 1 (SIP1, SOP1)
and Channel 2 (SIP2, SOP2), respectively.
Since other synchronous signal input pins SYNCA1 and SYNCA 2 for ADPCM interfaces are also
provided, the PCM and ADPCM data can be input or output with different timing.
PCM and ADPCM data interfaces can be used at a mutually independent timing except same
timing.
Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Notes on Usage" should not be used.
BCLKP
Bit clock input.
This signal defines the PCM data transmission speed at the PCM data input/output pins.
BCLKP is used for Channels 1 and 2. Since BCLKA defines the data rate of the ADPCM data
interface, the PCM and ADPCM data can be input or output at different speeds.
LAW
PCM data companding law (A-law/m-law) selection.
Digital “1” and “0” correspond to A-law and µ-law, respectively.
PDN1, PDN2
Power down mode selection.
PDN1 and PDN2 can be independently set to power down mode. When a digital “0” is applied,
these pins are in the power-down mode.
SIA1, SOA1
ADPCM serial data input (SIA1) and output (SOA1) pins for Channel 1.
SOA1 is an open-drain pin and enters to the high impedance state after outputting a continuous
4-bit serial data stream. When the data-through mode is selected, SOA1 enters to the high
impedance state after outputting an 8-bit serial data stream.
SIA2, SOA2
ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2.
These pins function the same as SIA1 and SOA1.
5/17
5 Page 
¡ Semiconductor
MSM7580
THR Processing Timing
Timing Block Diagrams, when CODER and DECODER output data, are shown in the following
figures.
The parallel to serial conversion of the output unit employs a load format and the load point is
at the rising edge of a synchronous signal.
Therefore, input THR signal with respect to SYNCA for CODER with timing of satisfying ts and
th conditions shown in the figure.
For DECODER, THR signal should be input even when through-data is input.
The input timing should satisfy the conditions shown in the following figures.
CODER
SYNCP
SIP
BCLKP
THR
Serial 8
Parallel
Latch
Latch timing=A
PCM side SYNC (SYNCP)
PCM Input (SIP)
MSB
Internal Latch timing (A)
Through-data
8b
ADPCM
CODER
S
E
L
4b
Parallel
Serial
LSB
SYNCA
SOA
BCLKA
Internal Input Data
Through-data
ADPCM side SYNC (SYNCA)
Through-data Output (SOA)
BCLKA
MSB
THR
ts
th
ts=100ns or more
th=100ns or more
Note: That data-ship may occur when the rising edge (data load point) of SYNCA and input of
the internal latch timing overlap each other.
11/17
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MSM7580.PDF ] | |
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