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PDF MSM7581 Data sheet ( Hoja de datos )
| Número de pieza | MSM7581 | |
| Descripción | ITU-T G.721 4ch ADPCM TRANSCODER | |
| Fabricantes | OKI | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MSM7581 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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E2U0032-28-82
¡¡SemicondSucetormiconductor
MSM7581
ITU-T G.721 4ch ADPCM TRANSCODER
This version: AMugS.M19795881
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7581 is an ADPCM transcoder which is used by the new digital cordless system.
It converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice
versa.
This device is consists of four systems with full-duplex voice data channels and a data-through
mode.
The MSM7581 provides cost effective solutions for digital cordless office telephone systems
which are incorporated into PABXs, and for the public base stations which are connected to the
Central Office through digital PSTNs.
FEATURES
• Conforms to ITU-T G.721
• Built-in Full-duplex Transcoder with Four Data Channels
• PCM companding Law: A-law/µ-law selectable
• Serial PCM Data Transmission Speed: 64 kbps to 2048 kbps
• Serial ADPCM Data Transmission Speed: 32 kbps to 2048 kbps
• Hardware Reset – ITU-T G.721 Optional Reset – for each channel
• Power Down Control for each channel
• Decoder (ADPCM Æ PCM ) Mute Mode and PAD Mode for each channel
• ADPCM Data-through Mode
• Capable of time slot conversion
• Special ADPCM Input Data Code (”0000”) Detector for each channel
• Master Clock Signal : Not necessary
• Power supply voltage/Consumption current :
+2.7 V to +5.5 V, 2 mA/channel (max)
• Package :
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7581TS-K)
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1 page  
¡ Semiconductor
MSM7581
THR1, THR2, THR3, THR4
Control pins for the data-through modes.
THR (1 - 4) are for Channel (1 - 4), respectively. The data-through mode is selected when digital
“1” is applied to THR (1 - 4). In this mode, 8-bit serial input data applied to SIA (1 - 4) (ADPCM
data input) is passed to the PCM serial data output pins, SOP (1 - 4), without any data
modification. SOP (1 - 4) go to the high impedance state after the output of 8-bit data has been
applied to SIA (1 - 4).
Conversely 8-bit serial input data applied to SIP (1 - 4) (PCM data input) is passed to ADPCM
serial data output pins, SOA (1 - 4), without any data modification.
SOA (1 - 4) go to the high impedance state after the output of 8-bit serial data has been applied
to SIP (1 - 4).
ADPCM and PCM data interfaces have the mutually independent signal input pins for
synchronizing signals. The time slots for data input and output can be exchanged between them.
Some timing at which data may be deleted or duplicated as described in "Note on Usage" should
not be used.
SYXP1 - 4, SYRP1 - 4
Synchronous signal input pins to define PCM data input and output timing for Channel 1 (SIP1,
SOP1), Channel 2 (SIP2, SOP2), Channnel 3 (SIP3, SOP3), and Channel 4 (SIP4, SOP4).
The synchronous signals SYXA1 and SYRAI (Channel 1), SYXA2 and SYRA2 (Channel 2),
SYXA3 and SYRA3 (Channel 3), and SYXA4 and SYRA4 (Channel 4), which define ADPCM data
input and output timing are provided.
PCM and ADPCM data interfaces can be used at a mutually independent timing except some
timing.
Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Note on Usage" should not be used.
SYXP signals must be input for PAD signal input processing.
BCKP1 - 4
Bit clock input.
These signals define the PCM data transmission speed at the PCM data input/output terminals.
BCKP (1 - 4) are used for Channel (1 - 4). Since BCKA (1 - 4) defines the data rate of the ADPCM
data interface, the PCM and ADPCM data can be input or output at different speeds.
LAW
PCM data companding law selection.
Digital “1” and “0” correspond to A-law and µ-law, respectively.
PDN1, PDN2, PDN3, PDN4
Power down mode selection.
PDN1 - 4 can be independently set to power down mode. When digital “0” is applied, these pins
are in the power-down mode.
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¡ Semiconductor
PAD Processing Timing
SYXA
BCKA
SIA MSB
78.125ms
LSB
Internal 12dBPAD processing Timing
121.09ms
Internal MUTE processing Timing
78.125ms
78.125ms
MSM7581
PAD10 to PAD40, PAD11 to PAD41 Timings
SYXP
PAD10, 11
ts
th
ts=100ns or more
th=100ns or more
Internal PAD
Signal
BCKP
SOP
MSB
0dB transmit data
LSB
PAD processing transmit data
0dB transmit data
As mentioned above, PAD and MUTE processings are performed according to the rising edge
of SYXA. Even if BLOCK is not 128 kHz, these processings are performed in the absolute time
counted from the rising edge of SYXA.
The PAD pin must be controlled so as to cover these processings.
The PAD signal is input in the device at the rising edge of SYXP. Therefore, the PAD signal should
be input at ts and th for the rise of SYXP.
11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MSM7581.PDF ] | |
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