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PDF CXD1199AQ Data sheet ( Hoja de datos )
| Número de pieza | CXD1199AQ | |
| Descripción | CD-ROM DECODER | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD1199AQ
CD-ROM DECODER
For the availability of this product, please contact the sales office.
Description
The CXD1199AQ is a CD-ROM decoder LSI with a
100 pin QFP (Plastic)
built-in ADPCM decoder.
Features
• Supports CD-ROM, CD-I and CD-ROM XA formats
• Real-time error correction
• Supports double speed playback
• Connectable with standard SRAM of up to 1 M-bits
(128 K-byte)
• All audio output sampling frequencies : 132.3 kHz
(built-in oversampling filter)
• De-emphasis digital filter
• Digital attenuator
• Intel CPU 80 series host interface
• Operates on 3.5 V
Applications
CD-ROM drives
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VDD –0.5 to +7.0 V
• Input voltage
VI –0.5 to VDD +0.5 V
• Output voltage
VO –0.5 to VDD +0.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
VDD +3.5 to +5.5
(+5.0 typ.)
• Operating temperature Topr –20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E93Z06A78-TE
1 page  
CXD1199AQ
Pin No.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
MDB4
MDB5
MDB6
MDB7
MDBP
XTL2
XTL1
VDD
GND
CLK
HCLK
CKSL
RMCK
LRCK
DATA
BCLK
C2PO
EMP
XRST
GND
DATO
LRCO
WCKO
BCKO
MUTE
TD7
TD6
TD5
TD4
TD3
I/O Description
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus (for error flag)
O Crystal oscillation circuit output
I Crystal oscillation circuit output (16.9344 MHz)
— Power supply (+5 V)
— GND
O 16.9344 MHz clock output
O 8.4672 MHz clock output
I Clock select signal for CD-ROM decoder
I Clock signal for CD-ROM decoder
I LR clock signal from CD DSP (for discriminating L, R channels)
I Data signal from CD DSP
I DATA pin strobe clock signal (bit clock)
I Error flag (C2 pointer) positive logic signal from CD DSP
I Emphasis ON positive logic signal from CD DSP
I Reset negative logic signal
— GND
O Data signal to DAC (D/A converter)
O LR clock signal to DAC
O Word clock signal to DAC
O Bit clock signal to DAC
O Mute positive logic signal
I/O Test I/O
I/O Test I/O
I/O Test I/O
I/O Test I/O
I/O Test I/O
—5—
5 Page 
CXD1199AQ
3. Host interface
(1) Read
HA0, 1
XHCS
XHRD
HD7 to 0, P
Thrd1
Thhar
Thsar
Thdrd
Thfrd
Item
Address setup time (for XHCS & XHRD ↓)
Address hold time (for XHCS & XHRD ↑)
Data delay time (for XHCS & XHRD ↓)
Data float time (for XHCS & XHRD ↑)
Low level XHRD pulse width
Symbol
Thsar
Thhar
Thdrd
Thfrd
Thrd1
Min.
30 (70)
20 (50)
0
100 (150)
Typ.
Max.
60 (100)
15 (25)
Unit
ns
ns
ns
ns
ns
(2) Write
HA0, 1
XHCS
XHWR
HD7 to 0, P
Thww1
Thhar
Thsar
Thswd Thhwd
Item
Address setup time (for XHCS & XHWR ↓)
Address hold time (for XHCS & XHWR ↑)
Data setup time (for XHCS & XHWR ↑)
Data hold time (for XHCS & XHWR ↑)
Low level XHWR pulse width
Symbol
Thsar
Thhar
Thswd
Thhwd
Thww1
Min.
30 (70)
20 (50)
40 (70)
10 (30)
60 (100)
Typ.
Max.
Unit
ns
ns
ns
ns
ns
—11—
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet CXD1199AQ.PDF ] | |
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