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PDF CXD1196 Data sheet ( Hoja de datos )
| Número de pieza | CXD1196 | |
| Descripción | CD-ROM DECODER | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD1196AR
CD-ROM DECODER
For the availability of this product, please contact the sales office.
Description
The CXD1196AR is a CD-ROM decoder LSI with a
built-in ADPCM decoder.
80 pin LQFP (Plastic)
Features
• CD-ROM, CD-I and CD-ROM XA format
compatible
• Real time error correction
• Double speed playback compatible
(when VDD=5.0±10 %)
• Can be connected to a standard SRAM up to 32
Kbytes (256 Kbits).
• All audio output sampling frequency : 132.3 kHz
(Built-in oversampling filter)
• Built-in de-emphasis digital filter
• Capable of VDD 3.5 V operation
Applications
CD-ROM drive
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD VSS –0.5 to +7.0 V
• Input voltage
VI VSS –0.5 to VDD +0.5 V
• Output voltage VO VSS –0.5 to VDD +0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
VDD +3.5 to +5.5 (+5.0 Typ.) V
• Operating temperature
Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92128B78-TE
1 page  
CXD1196AR
Electrical Characteristics
DC characteristics
Item
TTL input level pin (∗1)
input voltage H level
TTL input level pin (∗1)
input voltage L level
CMOS input level pin (∗2)
input voltage H level
CMOS input level pin (∗2)
input voltage L level
TTL schmitt input level pin (∗3)
input voltage H level
TTL schmitt input level pin (∗3)
input voltage L level
TTL schmitt input level pin (∗3)
input voltage hysteresis
CMOS schmitt input level pin (∗4)
input voltage H level
CMOS schmitt input level pin (∗4)
input voltage L level
CMOS schmitt input level pin (∗4)
input voltage hysteresis
Pull-up resistor provided input pin
(∗5) input current
Pull-down resistor provided input pin
(∗6) input current
Pull-up resistor provided bidirectional
pin (∗7) input current
Output voltage H level (∗8)
Output voltage L level (∗8)
Input leak current (∗9)
Oscillation cell (∗10) input voltage
H level
Oscillation cell input voltage L level
Oscillation cell logic threshold value
Oscillation cell feedback
resistance value
Oscillation cell output voltage H level
Oscillation cell output voltage L level
Symbol
VIH1
(VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C)
Conditions
Min. Typ. Max. Unit
2.2 V
VIL1 0.8 V
VIH2
0.7 VDD
V
VIL2 0.3 VDD V
VIH3
2.2
V
VIL3
VIH3
–VIL3
VIH4
0.4
0.8 VDD
0.8
V
V
V
VIL4
VIH4
–VIL4
IIL1
VIN=0 V
0.2 VDD V
0.6 V
–40 –100 –240 µA
IIL2 VIN=0 V
40 100 240 µA
IIL3
VOH1
VOL1
IIL2
VIH4
VIL4
LVTH
RFB
VOH2
VOL2
VIN=0 V
–90 –200 –440
VOH=–2 mA
IOL=4 mA
VDD–0.8
–40
0.4
40
0.7 VDD
0.3 VDD
0.5 VDD
VIN=VSS or VDD 500 K 1 M
2M
IOH=–3 mA
IOL=3 mA
0.5 VDD
0.5 VDD
µA
V
V
µA
V
V
V
Ω
V
V
—5—
5 Page 
CXD1196AR
3. DSP Interface for CD
BCKRED= “H”
BCLK
DATA
LRCK
C2PO
Tbck
Tbck
Tsb1
Thb1
Thb2
Tsb2
BCKRED= “L”
BCLK
Tbck
Tbck
DATA
LRCK
C2PO
Tsb1
Item
BCLK frequency
BCLK pulse width
Data setting time (with respect to BCLK)
Data holding time (with respect to BCLK)
LRCK, C2PO setting time (with respect to BCLK)
LRCK, C2PO holding time (with respect to BCLK)
Thb1
Thb2
Symbol
Fbck
Tbck
Tsb1
Thb1
Tsb2
Thb2
Min.
85
50
50
50
50
Thb2
Typ.
Max.
5.7
Unit
MHz
ns
ns
ns
ns
ns
—11—
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CXD1196.PDF ] | |
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