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PDF CY7C53150L Data sheet ( Hoja de datos )
| Número de pieza | CY7C53150L | |
| Descripción | 3.3V Neuron Chip Network Processor | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C53120L8
CY7C53150L
3.3V Neuron® Chip Network Processor
Features
• 3.3V operation
• Three 8-bit pipelined processors for concurrent
processing of application code and network traffic
• Hardware UART/SPI interface
• Eleven-pin I/O port programmable in 38 modes for fast
application program development. I/O port is 5V input
tolerant
• Two 16-bit timer/counters for measuring and gener-
ating I/O device waveforms
• Five-pin communication port that supports direct
connect and network transceiver interfaces, and
operates at 3.3V or 5V
• Programmable pull-ups on IO4–IO7 and 20-mA sink
current on IO0–IO3
• Unique 48-bit Neuron ID number in every device to facil-
itate network installation and management
• 0.35-µm Flash process technology
• On-chip LVD circuit with programmable trip point and
digital filter settings
• Programmable Pulse Stretching reset
• 4,096 bytes of SRAM for buffering network data,
system, and application data storage
• 2.75 KBytes (CY7C53150L), 8KBytes (CY7C53120L8) of
Flash memory with on-chip charge pump for flexible
storage of configuration data and application code
• Addresses up to 56 KBytes of external memory
(CY7C53150L)
• 16 KBytes (CY7C53120L8) of ROM containing LonTalk
network protocol firmware
• Maximum input clock operation of 20MHz over –40°C
to 85°C[1] temperature range
• 64-pin TQFP package (CY7C53150L)
• 32-pin SOIC or 44-pin TQFP package (CY7C53120L8)
Logic Block Diagram
Media Access
Control Processor
Functional Description
The 3.3V Neuron chip (CY7C53120L8/3150L) is a low-power
version of the 5V Neuron chip with a number of feature
enhancements. The CY7C53120L8/3150L Neuron chip imple-
ments a device for LonWorks distributed intelligent control
networks. It incorporates, on a single chip, the necessary
communication and control functions, both in hardware and
firmware, that facilitate the design of a LonWorks device.
The CY7C53120L8/3150L supports all the functionality of the
5V CY7C531x0 Neuron chip. Additionally it features 4KBytes
of RAM, 8KBytes of Flash memory (CY7C53120L8), and
hardware UART/SPI. The CY7C53120L8/3150L has an 11-pin
configurable I/O block. The I/Os are all 5V-tolerant to allow
interfacing to TTL Compatible 5V components and microcon-
trollers.
The CY7C53120L8/3150L contains a very flexible five-pin
communication port that can be configured to interface with a
wide variety of media transceivers at a wide range of data
rates. The communication port can operate at either 3.3V or
5V. In 5V mode the communication port is completely
backward compatible with existing 5V transceivers. The most
common transceiver types are twisted-pair, powerline, RF, IR,
fiber-optics, and coaxial.
The CY7C53150L incorporates an external memory interface
that can address up to 56KBytes with 8KBytes of the address
space mapped internally. LonWorks devices that require large
application programs can take advantage of this external
memory capability.
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware-based protocol
stored in 16KBytes ROM (CY7C53120L8), or off-chip memory
(CY7C53150L). The firmware also contains 38 prepro-
grammed I/O drivers, simplifying application programming.
The application program is stored in the Flash memory
(CY7C53120L8) and/or off-chip memory (CY7C53150L), and
may be updated by downloading over the network.
Communications
Port
CP4
CP0
Network
Processor
Application
Processor
4KBytes RAM
Flash
ROM
(CY7C53120L8)
Internal
Data Bus
(0:7)
Internal
Address Bus
(0:15)
Two Timer/Counters
4-pin UART/SPI
IO10
:
IO7
I/O Block
Oscillator,
Clock, and
Control
CLK1
CLK2
IO6
:
IO0
SERVICE
RESET
External Address and
Data Bus (CY7C53150L)
Note:
1. Maximum junction temperature is 105°C. TJunction = TAmbient + V•I•θJA. 32-pin SOIC θJA = 61.07°C/W. 44-pin TQFP θJA = 69.5°C/W. 64-pin TQFP θJA = 56.15°C/W.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-10002 Rev. *E
Revised November 2, 2004
1 page  
CY7C53120L8
CY7C53150L
able to aggregate writes to eight successive address locations
into a single write for CY7C53120L8 devices. For example, if
8KBytes of code is downloaded over the network, the firmware
would execute only 1024 writes rather than 8,192.
Manufacturer ID
The manufacturer ID is 0x02 for both the CY7C53150L and
CY7C53120L8. The major model ID is 0x02 for the
CY7C53150L and 0x10 for the CY7C53120L8. The minor
model ID is 0x08 for both ICs.
Low-Voltage Inhibit (LVI) Operation
The on-chip Low-voltage Inhibit circuit trips the Neuron chip
reset circuit whenever the VDD input drops below a set value.
The default value of the LVI trip point is 2.77V, with a variation
of ±100mV across process and temperature. Every time power
is reapplied to the chip, the LVI trip point gets set to this default
value. Through the application code, the trip point can be
programmed to be one of 16 points between 2.77V and 3.19V.
The purpose of the LVI circuit is to prevent the corruption of
nonvolatile memory during voltage drops. A lower value of trip
point voltage decreases the likelihood of the LVI tripping due
to noise on VDD. A lower setting is therefore recommended for
circuits with a lot of noise on the power supply. In circuits that
do not have excessive noise it is recommended that the LVI
trip point be increased which results in better flash protection
in case of real power loss scenarios.
Internal circuitry is provided to ensure that in a power loss
scenario, writes to non-volatile memory that have already
started get completed. To ensure proper functioning of this
circuitry, the VDD droop time (during power down or power
loss) should be at least 10ms from the time LVI circuit trips and
voltage reaches 2.77V.
The LVI also features a programmable digital filter used to filter
out VDD noise. This is another method of decreasing the possi-
bility of the LVI being triggered by the noise as opposed to true
power loss events. The digital filter is programmable to a value
between 16 and 128 clock cycles. The value chosen depends
on the frequency of the VDD noise where the digital filter period
should slightly exceed the minimum frequency noise seen on
VDD. The LVI digital filter defaults to 128 clock cycles.
Reset Stretching
Hardware Serial Communication Engine
The CY7C53120L8/3150L features a hardware Serial
Communication Engine. The hardware engine is capable of
performing high-speed communications in either SPI or UART
mode.
Serial Peripheral Interface (SPI) Mode
SPI mode is 4-pin synchronous serial communications
interface that can be set as either a Master or a Slave[6].
SPI Pin
IO7
IO8
IO9
IO10
Description
Slave Select (SS)
Hardware SPI Serial Clock (SPSCK)
Master Input/Slave Output (MISO)
Master Output/Slave Input (MOSI)
SPI communication is a point-to-point or point-to-multi-point
interface that can be configured as master/slave, single-
master/multiple-slaves or multiple-masters/single-slave. The
master initiates all communication between slave and master.
The master drives the SPSCK signal, which is a clock used to
synchronize all data communication between master and
slave.
Slave Select (SS) is an input to the Neuron chip in both the
Master and the Slave modes. In Slave mode, SS is active low
with the Slave communicating only when SS is low. In Master
mode, the SPI engine functions only when the SS signal is
held high. SS can be hard wired high or low or it can be wired
to signals being generated from other sources. The Neuron
Chip can use IO0 through IO6 for selecting between multiple
slaves when acting as a master.
MOSI and MISO are used to send and receive data over SPI.
MOSI is a data output in Master mode and is an input in Slave
mode. MISO is an input in Master mode and is an output in
Slave mode. The phase and polarity of the data relative to the
clock signal is programmable and can be configured in four
possible modes.
The SPI interface can communicate at a maximum of 5Mbps
data rate with a 20-MHz input clock frequency. The maximum
data rate scales with frequency. The data rate is program-
mable and can be scaled by selecting the desired divisor
ranging from 2 to 256 in multiples of 2.
At Power-on, the CY7C53120L8/3150L provides internal
Reset Stretching of 25ms at 20MHz clock frequency. Power-on
Reset Stretch time scales with frequency. After Power-on,
Reset Stretch is 50ms independent of frequency of operation.
At Power-on the CY7C53120L8/3150L defaults to Reset
Stretch enabled. The Reset Stretch can either be left enabled
or disabled through software. Reset Stretching eliminates the
need for an external pulse stretching LVI which is required
when using the CY7C53150 with an external Flash memory.
5V-Tolerant Reset
Serial Communication Interface (UART) Mode
UART mode provides a full-duplex asynchronous NRZ format
serial interface for communicating with other devices with
either an UART or UART interface. The UART interface is
optimized to provide industry standard UART baud rates from
the CY7C53120L8/3150L crystal clock rates.
UART Pin
Description
IO8 Receive Data (RXD)
IO10
Transmit Data (TXD)
RESET is an Input/Output pin. It is a 5V-tolerant input pin. It
can provide 5V-compatible levels when output if an external
resistor is connected between pin and 5V supply.
Note:
6. Please see document Errata for CY7C53150L and CY7C53120L8 - 3.3V Neuron Chip (38-17019) for details.
Document #: 38-10002 Rev. *E
Page 5 of 14
5 Page 
CY7C53120L8
CY7C53150L
Voltage
4
3
Vcm
2
V(CP0)
V(CP1)
Voltage
1
Vh
-1
V(CP0)-V(CP1)
Vtrip+
Vtrip-
Time
Time
Neuron
Chip's
Internal
Comparator
5V
0V
Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2
Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 8. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 5V Operation
Voltage
3
2
Vcm
1
V(CP0)
V(CP1)
Voltage
0.5
V(CP0)-V(CP1)
Vh
Vtrip+
Vtrip-
Time
Time
-0.5
Neuron
Chip's
Internal
Comparator
3.3V
0V
Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2
Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 9. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 3.3V Operation
Document #: 38-10002 Rev. *E
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C53150L.PDF ] | |
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