PDF CY7C4291 Data sheet ( Hoja de datos )

Número de pieza	CY7C4291
Descripción	64K/128K x 9 Deep Sync FIFOs
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C4281 CY7C4291 64K/128K x 9 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 64K × 9 (CY7C4281) • 128K × 9 (CY7C4291) • 0.5-micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC= 40 mA — ISB = 2 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Output Enable (OE) pin • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • 32-pin PLCC • Pin-compatible density upgrade to CY7C42X1 family • Pin-compatible density upgrade to IDT72201/11/21/31/41/51 Logic Block Diagram D0 − 8 INPUT REGISTER Functional Description The CY7C4281/91 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4281/91 are pin-compatible to the CY7C42X1 Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor inter- faces, and communications buffering. These FIFOs have nine-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4281/91 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. Pin Configuration PLCC Top View WCLK WEN1 WEN2/LD WRITE CONTROL WRITE POINTER Dual Port RAMARRAY 64K x 9 128K x 9 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER EF PAE PAF FF D1 D0 PAF PAE GND REN1 RCLK REN2 OE 4 3 2 1 32 31 30 5 29 6 28 7 27 8 CY7C4281 26 9 10 CY7C4291 25 24 11 23 12 22 13 21 14 15 16 17 18 19 20 RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 RS RESET LOGIC THREE-STATE OUTPUT REGISTER Q0 – 8 OE READ CONTROL RCLK REN1 REN2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-06007 Rev. B Revised August 19, 2003 1 page CY7C4281 CY7C4291 RESET (RS) DATA IN (D) 18 9 WRITECLOCK (WCLK) WRITE ENABLE 1(WEN1) WRITE ENABLE 2/LOAD (WEN2/LD) PROGRAMMABLE(PAF) CY7C4281/91 FULL FLAG (FF) # 1 FF EF FULL FLAG (FF) # 2 9 Read Enable 2 (REN2) RESET (RS) 9 READ CLOCK (RCLK) READ ENABLE 1 (REN1) CY7C4281/91 OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 FF EF 9 DATA OUT (Q) 18 Read Enable 2 (REN2) Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration Notes: 2. n = Empty Offset (n = 7 default value). 3. m = Full Offset (m = 7 default value). Document #: 38-06007 Rev. B Page 5 of 16 5 Page Switching Waveforms (continued) Empty Flag Timing WCLK D0 –D8 tDS DATA WRITE 1 tENH WEN1 WEN2 (if applicable) tENS tENS tENH tFRL [18] RCLK tSKEW1 EF tREF REN1, REN2 OE LOW Q0 –Q8 DATA IN OUTPUT REGISTER CY7C4281 CY7C4291 tDS DATA WRITE 2 tENS tENH tENS tENH tFRL[18] tREF tSKEW2 tREF tA DATA READ Document #: 38-06007 Rev. *B Page 11 of 16 11 Page

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