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PDF AD9772A Data sheet ( Hoja de datos )
| Número de pieza | AD9772A | |
| Descripción | 14-Bit 160 MSPS TxDAC+ | |
| Fabricantes | Analog Devices | |
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FEATURES
Single 3.1 V to 3.5 V supply
14-bit DAC resolution and input data width
160 MSPS input data rate
67.5 MHz reconstruction pass band @ 160 MSPS
74 dBc SFDR @ 25 MHz
2× interpolation filter with high- or low-pass response
73 dB image rejection with 0.005 dB pass-band ripple
Zero-stuffing option for enhanced direct IF performance
Internal 2×/4× clock multiplier
250 mW power dissipation; 13 mW with power-down mode
48-lead LQFP package
APPLICATIONS
Communication transmit channel
W-CDMA base stations, multicarrier base stations,
direct IF synthesis, wideband cable systems
Instrumentation
GENERAL DESCRIPTION
The AD9772A is a single-supply, oversampling, 14-bit digital-
to-analog converter (DAC) optimized for baseband or IF
waveform reconstruction applications requiring exceptional
dynamic range. Manufactured on an advanced CMOS process,
it integrates a complete, low distortion 14-bit DAC with a 2×
digital interpolation filter and clock multiplier. The on-chip PLL
clock multiplier provides all the necessary clocks for the digital
filter and the 14-bit DAC. A flexible differential clock input
allows for a single-ended or differential clock driver for
optimum jitter performance.
For baseband applications, the 2× digital interpolation filter
provides a low-pass response, thus providing as much as a
threefold reduction in the complexity of the analog reconstruc-
tion filter. It does so by multiplying the input data rate by a
factor of 2 while suppressing the original upper in-band image
by more than 73 dB. For direct IF applications, the 2× digital
interpolation filter response can be reconfigured to select the
upper in-band image (that is, the high-pass response) while
suppressing the original baseband image. To increase the signal
level of the higher IF images and their pass-band flatness in
direct IF applications, the AD9772A also features a zero-stuffing
option in which the data following the 2× interpolation filter is
upsampled by a factor of 2 by inserting midscale data samples.
14-Bit, 160 MSPS TxDAC+
with 2× Interpolation Filter
AD9772A
FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
CLK+
CLK–
AD9772A
CLOCK DISTRIBUTION
AND MODE SELECT
PLL CLOCK
MULTIPLIER
1×
1×/2×
FILTER
CONTROL
MUX
CONTROL
2×/4×
PLLCOM
LPF
PLLVDD
DATA
INPUTS
(DB13 TO
DB0)
SLEEP
EDGE-
TRIGGERED
LATCHES
2× FIR
INTER-
POLATION
FILTER
ZERO-
STUFF
MUX
14-BIT DAC
1.2V REFERENCE
AND CONTROL AMP
IOUTA
IOUTB
REFIO
FSADJ
DCOM DVDD
ACOM AVDD
Figure 1.
REFLO
The AD9772A can reconstruct full-scale waveforms with band-
widths of up to 67.5 MHz while operating at an input data rate
of 160 MSPS. The 14-bit DAC provides differential current
outputs to support differential or single-ended applications.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current
outputs can be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an
appropriate resistive load.
The on-chip band gap reference and control amplifier are con-
figured for maximum accuracy and flexibility. The AD9772A
can be driven by the on-chip reference or by a variety of
external reference voltages. The full-scale current of the
AD9772A can be adjusted over a 2 mA to 20 mA range, thus
providing additional gain-ranging capabilities.
The AD9772A is available in a 48-lead LQFP package and is
specified for operation over the industrial temperature range of
–40°C to +85°C.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
AD9772A
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
Monotonicity (12-Bit)
ANALOG OUTPUT
Offset Error
Gain Error
Without Internal Reference
With Internal Reference
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (REFLO = 3 V)
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift
Without Internal Reference
With Internal Reference
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (IAVDD)
Analog Supply Current in Sleep Mode (IAVDD)
DVDD
Voltage Range
Digital Supply Current (IDVDD)
CLKVDD, PLLVDD4 (PLLVDD = 3.3 V)
Voltage Range
Clock Supply Current (ICLKVDD + IPLLVDD)
Min Typ Max
14
±3.5
±2.0
Guaranteed over specified temperature range
−0.025
+0.025
−2 ±0.5 +2
−5 ±1.5 +5
20
−1.0 +1.25
200
3
1.14 1.20 1.26
1
0.1 1.25
10
0.5
0
±50
±100
±50
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
μA
V
MΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
3.1 3.3 3.5 V
34 37
mA
4.3 6
mA
3.1 3.3 3.5 V
37 40
mA
3.1 3.3 3.5 V
25 30
mA
Rev. C | Page 4 of 40
5 Page 
AD9772A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
DCOM 1
DCOM 2
(MSB) DB13 3
DB12 4
DB11 5
DB10 6
DB9 7
DB8 8
DB7 9
DB6 10
DB5 11
DB4 12
PIN 1
IDENTIFIER
AD9772A
TOP VIEW
(Not to Scale)
36 SLEEP
35 LPF
34 PLLVDD
33 PLLCOM
32 CLKVDD
31 CLKCOM
30 CLK–
29 CLK+
28 DIV0
27 DIV1
26 RESET
25 PLLLOCK
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 19, 20 DCOM
Digital Common.
3
DB13
Most Significant Data Bit (MSB).
4 to 15
DB12 to DB1 Data Bit 1 to Data Bit 12.
16 DB0 Least Significant Data Bit (LSB).
17
MOD0
Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is,
half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin
are set high.
18
MOD1
Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing
occurs if this pin and the MOD0 pin are set high.
23, 24
NC
No Connect. Leave open.
21, 22, 47, 48 DVDD
Digital Supply Voltage (3.1 V to 3.5 V).
25
PLLLOCK
Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL
clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High
indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF).
26
RESET
Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input
data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when
PLL is disabled.
27, 28
DIV1, DIV0 PLL Prescaler Divide Ratio. DIV1 and DIV0 set the prescaler divide ratio of the PLL (refer to Table 10).
29
CLK+
Noninverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
30
CLK−
Inverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2).
31
CLKCOM
Clock Input Common.
32
CLKVDD
Clock Input Supply Voltage (3.1 V to 3.5 V).
33
PLLCOM
Phase-Lock Loop Common.
34
PLLVDD
Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable the PLL clock multiplier, connect PLLVDD to
PLLCOM.
35 LPF PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than
10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated in Figure 61.
36
SLEEP
Power-Down Control Input. Active high. When this pin is not used, connect it to ACOM.
37, 41, 44
ACOM
Analog Common.
38
REFLO
Reference Ground When Internal 1.2 V Reference Is Used. Connect this pin to AVDD to disable the internal
reference.
Rev. C | Page 10 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9772A.PDF ] | |
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