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PDF AS3502 Data sheet ( Hoja de datos )
| Número de pieza | AS3502 | |
| Descripción | 13-BIT LINEAR FEATURE CODEC WITH ANALOGUE FRONTEND | |
| Fabricantes | austriamicrosystems AG | |
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AS3502
Austria Mikro Systeme International AG
13-BIT LINEAR FEATURE CODEC
WITH ANALOGUE FRONTEND
Key Features
q 13-Bit Linear Sigma Delta Codec with Filters
Exceeding ETSI prETS30085 and G712 .
q Single Rail 3.0 V ~5.5 V Power Supply.
q Typical Power Dissipation of 30 mW at 3 V.
q Two Low Noise Microphone Inputs with Internal
Gain Adjust (+16 / +46 dB).
q 150Ω Push/Pull Earpiece Driver with Internal
Gain Adjust (-12 / +6 dB).
q 50Ω Loudspeaker Amplifier with up to 50 mW
Output Power.
q Push/ Pull Output Driver for Tone Ringer.
q On Chip Electret Microphone Voltage Source.
q Digital Transmit Gain Setting (-38 / +10 dB).
q Digital Receive Gain Setting ( -42 / +6 dB).
q Digital Sidetone Control Function ( 0 / -48 dB).
q Programmable Call Progress Tone/ DTMF /
Ring Tone Generator.
q Analogue and Digital Loopback Modes.
q 16-Bit Linear / 8-Bit A-Law Switchable Serial
PCM Interface with Non Delayed and Delayed
Timing Modes.
q 4-Wire Serial Control Interface.
q Packaged in SOIC-28, TQFP-64.
General Description
AS3502 is a high performance 13-bit linear feature
Codec/Filter with 8 kHz sampling rate specifically
tailored to implement all analogue frontend functions
of battery powered digital terminals. It includes a
programmable analogue interfaces for handset and
handsfree operation with a minimum amount of
external components.
The Codec function of AS3502 uses Sigma-Delta (Σ∆)
modulation conversion techniques with 2nd order
modulators and an over sampling rate of 128 for
excellent signal to noise performance. The AS3502
exceeds all CCITT G712 recommendations and the
European ETSI prETS 300085 recommendations.
Digital gain setting stages for transmit and receive
allow to compensate for transducer tolerances and to
set up a handsfree function under software control. A
programmable tone generator allows to generate
DTMF/Call-Progress Tones and alert sounds required
in digital terminals. All programmable functions of
AS3502 are controlled by a 4-wire serial control port
that easily interfaces to any popular micro controller.
The interface to the digital world is accomplished by a
serial PCM interface that supports 16-bit linear format
or 8-bit A-Law format for both non-delayed and
delayed frame synchronzation modes.
Block Diagramme
MIC2+
MIC2-
MIC1+
MIC1-
30Kž
AGX
+
16/46
dB
AAF
VREF
EP+
EP-
SPK+
SPK-
AGR
-12/+6
dB
+3dB
+
LPF
+
AS3502
VOICE
ADC
TONE
LOOP
Decimation
Filter
BPF
DGX
dB
-38/+10
Lin/A-
Comp.
PPCCMM
TTXX
-+
VREF
-+
SINE
SQ.
F1-F3,
V1-V3
Freq.
Gen.
S1, S2 CP, CP RP, RO
Seq.
Caden.
Rep.
SG
DC
dB
0/-48
Contr.
DAC
V2
DAC
LOOP
Interpolation
Filter
LPF
DGR
Lin/A-
dB +
-42/+6
Exp.
PPCCMM
TRX X
AGND
POR
Serial Control
TXD
TXS
MCLK
SCLK
RXS
RXD
GND DVDD
TRO- TRO+ AVDD CAP AVSS
POR
CS SCL SDI SDO
REV. M
Page 1
September 1998
1 page  
AS3502
Functional Description
Power-On Reset
When power is applied first a power on reset signal is
generated on chip which initializes AS3502:
The on chip programmable AFE registers are set to
their default values (those values are defined in the
register allocation section), the tone control register is
set to the default status and the serial interface is ini-
tialized. AS3502 remains in power down state until a
software start-up command. An active Low signal with
a duration of min. 25 µs on the power on reset pin can
be used to externally reset the device AS3502. For
normal operation this pin must be pulled High.
Power Up Mode
AS3502 is powered up through a one byte start-up
command. The byte written into the Digital Control
Register DC allows to individually enable the transmit
and the receive section. If the transmit channel is en-
abled first, the receive channel may be enabled any
time without any restrictions. On enabling the receive
channel and subsequent enabling of the transmit
channel the PCM strobe signals TXS and RXS have
to be tied together. The configuration information
written into the AC and AG define which analogue
transducer interfaces will be enabled on power up.
The PCM output TXD remains in Tristate until the
second frame synchronization signal after start-up.
Any of the programmable registers may be modified
while AS3502 is in active mode.
Power Down Mode
In power down mode all chip functions except the se-
rial interface are kept inactive. All analogue functions
are powered down and all digital outputs are put into
Tristate mode. In this operating state the internal
registers are normally configured to the desired
values prior to the start-up command. The chip can
be brought into power down mode any time through a
power down command written into the DC Register. In
this case all programmable registers retain their pro-
grammed values.
Analogue Input interface
The AS3502 input interface provides two identical dif-
ferential inputs e.g. for a handset microphone and for
a handsfree microphone. The input sources are se-
lected through the AG register. Clipping of signals
with arbitrary DC offset must be avoided by capacitive
coupling. The input impedance of 2 x 30 kΩ is
compatible with both electret and dynamic
microphones. Each input is connected through an
analogue input multiplexer to a low noise high gain
preamplifier. The gain is software programmable
through register AG from +16 to +46 dB in 6 dB steps
with a tolerance of ±0.2 dB. This wide range
guarantees optimum usage of the A/D converter dy-
namic range with various transducers.
Analogue Output Interface
The AS3502 output interface provides differential
outputs for an earpiece, for a loudspeaker and for a
toneringer. The output stages are selected through
the AC register. The earpiece output driver is a fully
differential amplifier that is capable of driving 3.2Vpp
into a 150Ω transducer directly and is gain
programmable in three steps from -12 dB to +6 dB
through the AG register. The +6 dB step allows to
drive ceramic earpiece transducers or to boost the re-
ceive amplitude. The loudspeaker driver is a fully
differential power amplifier with a peak output power
of 50 mW into a 50Ω loudspeaker. This output allows
loudhearing and handsfree operation under software
control.
The tone ringer outputs are digital push/pull outputs
with rail to rail voltage swing that capable of driving
various toneringers. For volume control the output
signal may be either pulse density modulated or pulse
width modulated under software control.
Transmit Section
The scaled analogue input signal enters a 1st order
RC antialiasing filter with a corner frequency of
approx. 40 kHz. This filter eliminates the need for any
off chip filtering as it provides sufficient attenuation at
1.024 MHz to avoid aliasing. From there the bandlim-
ited signal is fed to a 2nd order Sigma Delta modula-
tor with a sampling frequency of 1.024 MHz. A factory
trimmed voltage reference guarantees accurate
absolute transmit gain (0 dBm0 reference level). The
modulator is followed by a digital decimation filter that
transforms the resolution in time to resolution in
amplitude. The decimation filter is followed by a mini-
mum phase 5th order IIR filter implementing the
CCITT lowpass portion of the encoder bandpass fre-
quency characteristics. Finally a 3rd order IIR high
pass filter implements the highpass portion of the en-
coder bandpass frequency characteristics according
to CCITT specifications.
The digitally filtered signal is further fed to a digital
gain setting stage which allows to program the gain
from -38 to +10 dB with a tolerance of better than
±0.05 dB from 0 to +6 dB to compensate for
transducer sensitivity variations. The same stage may
additionally be used for digital volume control for
transmit volume attenuation. This feature may be
used for software based handsfree voice switching
algorithms.
In case of 16 bit linear mode the voice band signals
are converted to a PCM two's complement 12 data bit
plus sign bit format with a sample rate of 8 kHz and
REV. M
Page 5
September 1998
5 Page 
AS3502
1) DIGITAL CONTROL REGISTER
This register controls the master clock divider, the enabling of the transmit channel, the enabling of thereceive
channel and the PCM format.
DC D7 D6 D5 D4 D3 D2 D1 D0
Name
A/LIN
ENRX
ENTX
DIV3
DIV2
DIV1
DIV0
X
Default
0
0
0
0
0
0
0
X
Bit No
D7
D6
D5
D4- D1
Symbol Name and Description
A/LIN
A-Law / Linear Select. In default mode or when set to Low 16-bit linear PCM format is
selected. When set to High 8-bit A-Law PCM format is selected.
ENRX
Enable Receive Channel. When set to High the Receive Channel including the selected
output driver, the master clock divider and the Receive PCM interface are enabled.
When set to Low the Receive Channel will be powered down.
ENTX
Enable Transmit Channel. When set to High the Transmit Channel including the se-
lected microphone input, the master clock divider and the Transmit PCM interface are
enabled. When set to Low the Transmit Channel will be powered down.
DIV3-DIV0 Master Clock Prescaler Setting Bits.
DIV3 DIV2 DIV1 DIV0 State
Master Clock Frequency
0 0 0 0 ÷1
2.048 MHz
0 0 0 1 ÷2
4.096 MHz
0 0 1 0 ÷3
6.144 MHz
0 0 1 1 ÷4
8.192 MHz
0 1 0 0 ÷5
10.240 MHz
0 1 0 1 ÷6
12.288 MHz
0 1 1 0 ÷7
14.336 MHz
0 1 1 1 ÷8
16.386 MHz
1 0 0 0 ÷9
18.432 MHz
2) ANALOGUE CONTROL REGISTER
The Analogue Control Register enables the output drivers and the muting of the receive voice channel. Further it
allows to monitor clipping in both the transmit and the receive channel for software based automatic gain control.
AC
Name
Default
D7
0
0
D6 D5 D4 D3 D2 D1 D0
0
LOOP CLIPRX CLIPTX
ENEP
ENSPK
NOV
0000000
REV. M
Page 11
September 1998
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AS3502.PDF ] | |
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