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PDF NAU85L20 Data sheet ( Hoja de datos )

Número de pieza NAU85L20
Descripción Dual Audio ADC
Fabricantes nuvoton 
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NAU85L20 Data Sheet
NAU85L20
Dual Audio ADC with Integrated FLL and Microphone Preamplifier
Description
The NAU85L20 is a low power, high quality, 2-channel ADC for microphone array application. The NAU85L20
integrates programmable gain preamplifiers for stereo differential microphones, significantly reducing external
component requirements. A fractional FLL is available to accurately generate any audio sample rate using any
commonly available system clock source from 8KHz through 33MHz. Audio data can be directed to I2S data out
lines.
The NAU85L20 operates with analog supply voltages from 1.6V to 2V, while the digital core can operate down to
1.2V to conserve power. Internal register controls enable flexible power saving modes by powering down sub-
sections of the chip under software control. The NAU85L20 is specified for operation from -40°C to +85°C, and is
available in a 28-lead QFN package.
Features
101dB SNR (A-weighted) @ 0dB gain,
Supports sample rates from 8 kHz to 48 kHz at 24-
VDDA=1.8V, Fs = 48 kHz, OSR=128x
91dB THD+N @ 0dB gain, 0.8Vrms in,
VDDA=1.8V, Fs=48 kHz, OSR=128x
-124dB Channel Crosstalk @ 0dB gain, 0.9Vrms
in, VDDA=1.8V, Fs=48 kHz, OSR=128x
Integrated programmable gain microphone
amplifier
On-chip FLL
I2C Serial control interface with read/write
bit resolution
Two separate microphone bias supplies for low
noise microphone biasing.
Standard audio data bus interfaces: I2S, Left or
Right justified, Two’s compliment, MSB first
32-bit audio sub frames
Package: Pb free 28L-QFN
Temperature range: -40 to 85°
capability
Block Diagram
MIC1P
MIC1N
MIC2P
MIC2N
MICBIAS1
MICBIAS2
ADC Digital Core
HPF
NF
ADC ALC
u/A Law
Compression
MICBIAS 1
MICBIAS 2
FLL
Audio
Interface
I2S/PCM
BCLK
FS
DO12
I2C/SPI
SCLK
SDIO
CSB
MODE
Nuvoton Technology Corporation America
Tel: 1-408-544-1718
Fax: 1-408-544-1787
Rev. 0.1.6: May 10, 2016
1

1 page




NAU85L20 pdf
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
MIC2P/LIN2
MIC2N
VREF
MICREF
VDDC
VSSD
VDDB
MCLKO
NC
DO12
BCLK
FS
MCLKI
CSB
SCL
SDA
MODE
18 VDDA
19 VSSA
20 MIC1N
21 MIC1P/LIN1
22 NC
23 NC
24 MICBIAS1
25 MICVDD
26 MICBIAS2
27 NC
28 NC
NAU85L20
Type
Analog Input
Analog Input
Reference
Analog Output
Supply
Supply
Supply
Digital Output
Digital Output
Digital I/O
Digital I/O
Digital Input
Digital Input
Digital Input
Digital I/O
Digital Input
Supply
Supply
Analog Input
Analog Input
Functionality
MICP Input 2 / Line In Input 2
MICN Input 2
Decoupling for Mid-rail Reference Voltage
Decoupling for MIC Reference Voltage
Digital Core Supply
Digital Ground
Digital Buffer (Input/Output) Supply
Output from PLL
Digital Audio ADC Data Output for ADC 1 and 2
Digital Audio Bit Clock
Digital Audio Frame Sync
Master Clock Input
3-Wire MPU Chip Select/I2C address LSB
3-Wire MPU Clock Input/I2C Clock (SCL)
3-Wire MPU Data Input/I2C Data I/O (SDA)
Control Interface Mode Selection Pin (I2C=1,
SPI=0)
Analog Power Supply
Analog Ground
MICN Input 1
MICP Input 1 / Line In Input 1
Analog Output
Supply
Analog Output
Microphone Bias for Microphone ADC 1
Microphone Supply
Microphone Bias for Microphone ADC 2
Nuvoton Technology Corporation America
Tel: 1-408-544-1718
Fax: 1-408-544-1787
Rev. 0.1.9: May 10, 2016
5

5 Page





NAU85L20 arduino
NAU85L20
The polarity of either ADC output signal can be changed independently on either ADC logic output which can
be sometimes useful in management of the audio phase. This feature can help minimize any audio
processing that may be otherwise required as the data are passed to other stages in the system. The ADC
coding scheme is in twos complement format and the full-scale input level is proportional to VDDA. For
example, with a 1.8V supply voltage, the full-scale level is 1.0VRMS.
2.2.1 Input Limiter / Automatic Level Control (ALC)
The ADC digital path of the NAU85L20 is supported by the digital Automatic Level Control (ALC) function.
This can be used to automatically manage the gain to optimize the signal level at the output of the ADC by
automatically amplifying input signals that are too small or decreasing the amplitude of the signals that are too
loud.
The ALC monitors the output of the ADC, measured after the digital decimator. The ADC output is fed into a
peak detector, which updates the measured peak value whenever the absolute value of the input signal is
higher than the current measured peak. The measured peak gradually decays to zero unless a new peak is
detected, allowing for an accurate measurement of the signal envelope. The peak value is then used by a
logic algorithm to determine whether the gain should be increased, decreased, or remain the same.
In normal mode, when sudden peaks occur above the desired gain settings, the ALC reduces volume at a
register determined rate and step size. This continues until the output level of the ADC is again at the desired
target level. If the input signal suddenly becomes quiet, the ALC increases volume at a register determined
rate and step size until the output level from the ADC reaches the target level. If the input gain stays within
the target level, the ALC will remain in a steady state.
In addition to the normal operation mode, the ALC may be operated in a special limiter mode that functions
similarly to the normal mode but with faster attack times. This mode is primarily used to quickly ramp down
signals that are too loud.
2.2.1.1 ALC Peak Limiter Function
Both normal and limiter mode include a peak limiter function. This implements an emergency gain reduction
when the ADC output level exceeds a set gain value. When the ADC output exceeds 87.5% of full scale, the
ALC block ramps down the gain at the maximum ALC Attack Time rate. This is regardless of the mode and
attack rate settings. This continues until the ADC output level has been reduced to below the emergency limit
threshold. This action limits ADC clipping if there is a sudden increase in the input signal level.
2.2.1.2 ALC Parameter Definitions
ALC Maximum Gain (ALCMAX): This sets the maximum allowed gain during normal mode ALC operation. In
the Limiter mode of ALC operation, the ALCMXGAIN value is not used, instead, the maximum gain
allowed is set equal to the pre-existing gain value that was in effect at the moment in time that the Limiter
mode is enabled. See ALC_CONTROL_2 REG0X21 for details.
ALC Minimum Gain (ALCMIN): This sets the minimum allowed gain during all modes of ALC operation. This
is useful to keep the ALC operating range close to the desired range for a given application scenario.
See ALC_CONTROL_2 REG0X21 for details.
ALC Target Value (ALCLVL): Determines the value used by the ALC logic decisions comparing this fixed
value with the output of the ADC. This value is expressed as a fraction of Full Scale (FS) output from the
ADC. Depending on the logic conditions, either the output value used in the comparison may be the
instantaneous value of the ADC, or a time weighted average of the ADC peak output level. See
ALC_CONTROL_2 REG0X21 for details.
ALC Attack Time (ALCATK): Attack time refers to how quickly a system responds to an increasing volume
level that is greater than some defined threshold. Typically, attack time is much faster than decay time.
In the NAU85L20, when the absolute value of the ADC output exceeds the ALC Target Value, the gain
Nuvoton Technology Corporation America
Tel: 1-408-544-1718
Fax: 1-408-544-1787
Rev. 0.1.9: May 10, 2016
11

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