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PDF MCF52232 Data sheet ( Hoja de datos )
| Número de pieza | MCF52232 | |
| Descripción | ColdFire Microcontroller | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52235
Rev. 10, 3/2011
MCF52235
MCF52235 ColdFire
Microcontroller Data Sheet
Supports MCF52230, MCF52231,
MCF52232, MCF52233, MCF52234,
MCF52235, and MCF52236
The MCF52235 is a member of the ColdFire® family of
reduced instruction set computing (RISC) microcontrollers.
This document provides an overview of the MCF52235
microcontroller family, focusing on its highly integrated and
diverse feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 60 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to 256
Kbytes of Flash and 32 Kbytes of static random access
memory (SRAM). On-chip modules include:
• V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60
MHz executing out of on-chip Flash memory using
enhanced multiply accumulate (EMAC) and hardware
divider
• Enhanced Multiply Accumulate Unit (EMAC) and
hardware divide module
• Cryptographic Acceleration Unit (CAU) coprocessor
• Fast Ethernet Controller (FEC)
• On-chip Ethernet Transceiver (EPHY)
• FlexCAN controller area network (CAN) module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Inter-integrated circuit (I2C™) bus controller
• Queued serial peripheral interface (QSPI) module
• Eight-channel 10- or 12-bit fast analog-to-digital converter
(ADC)
• Four channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM) and pulse accumulation
• Eight/Four-channel 8/16-bit pulse width modulation timers
(two adjacent 8-bit PWMs can be concatenated to form a
single 16-bit timer)
LQFP-80
14mm x 14mm
LQFP-112
20mm_x_20mm
MAPBGA-121
12mm_x_12mm
• Two 16-bit periodic interrupt timers (PITs)
• Real-time clock (RTC) module
• Programmable software watchdog timer
• Two interrupt controllers providing every peripheral with a
unique selectable-priority interrupt vector plus seven
external interrupts with fixed levels/priorities
• Clock module with support for crystal or external oscillator
and integrated phase-locked loop (PLL)
• Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
1 page  
MCF52235 Family Configurations
1.2.1 Feature Overview
The MCF52235 family includes the following features:
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 60 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support 16 16 32 or 32 32 32
operations
— Cryptography Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions
– FIPS-140 compliant random number generator
— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into
a 1- or 2-level trigger
• On-chip memories
— Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power
supply support
— Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• Fast Ethernet Controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
• On-chip Ethernet Transceiver (EPHY)
— Digital adaptive equalization
— Supports auto-negotiation
— Baseline wander correction
— Full-/Half-duplex support in all modes
— Loopback modes
— Supports MDIO preamble suppression
— Jumbo packet
• FlexCAN 2.0B module
Freescale Semiconductor
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
5
5 Page 
MCF52235 Family Configurations
1.2.10 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the
interconnection between devices. This bus is suitable for applications requiring occasional communications over a short
distance between many devices on a circuit board.
1.2.11 QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.
It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.12 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding
separate 10- or 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed
scan sequence repeatedly until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight
channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a
scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This
configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low
threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.13 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the each device.
Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured
to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected,
it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual
timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.
Timer events may optionally cause interrupt requests or DMA transfers.
1.2.14 General Purpose Timer (GPT)
The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage
programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, one of
the channels, channel 3, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
The input capture and output compare functions allow simultaneous input waveform measurements and output waveform
generation. The input capture function can capture the time of a selected transition edge. The output compare function can
generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a
gated time accumulator.
Freescale Semiconductor
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCF52232.PDF ] | |
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