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PDF LPC11U23 Data sheet ( Hoja de datos )

Número de pieza LPC11U23
Descripción 32-bit ARM Cortex-M0 microcontroller
Fabricantes NXP Semiconductors　
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! LPC11U23 Hoja de datos, Descripción, Manual

LPC11U2x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up
to 10 kB SRAM and 4 kB EEPROM; USB device; USART
Rev. 2.3 — 27 March 2014
Product data sheet
1. General description
The LPC11U2x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U2x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the
LPC11U2x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to
10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface,
one RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC
(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.
For additional documentation related to the LPC11U2x parts, see Section 15
“References”.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
Up to 10 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) for flash and
EEPROM via on-chip bootloader software.
ROM-based USB drivers. Flash updates via USB supported.
ROM-based 32-bit integer division routines.
Debug options:

1 page




LPC11U23 pdf
NXP Semiconductors
6. Pinning information
6.1 Pinning
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
terminal 1
index area
PIO1_19/DTR/SSEL1
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
XTALIN
XTALOUT
VDD
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
1
2
3
4
5
6
7
8
LPC11U24
33 VSS
24 TRST/PIO0_14/AD3/CT32B1_MAT1
23 TDO/PIO0_13/AD2/CT32B1_MAT0
22 TMS/PIO0_12/AD1/CT32B1_CAP0
21 TDI/PIO0_11/AD0/CT32B0_MAT3
20 PIO0_22/AD6/CT16B1_MAT1/MISO1
19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2
18 PIO0_9/MOSI0/CT16B0_MAT1
17 PIO0_8/MISO0/CT16B0_MAT0
002aag621
Fig 2. Pin configuration (HVQFN33)
Transparent top view
LPC11U2X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.3 — 27 March 2014
© NXP B.V. 2014. All rights reserved.
5 of 74

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LPC11U23 arduino
NXP Semiconductors
Table 3. Pin description
Symbol
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
Reset Type Description
state
[1]
TRST/PIO0_14/AD3/
CT32B1_MAT1
24 B7 35 46 [6] I; PU
-
-
-
SWDIO/PIO0_15/AD4/
CT32B1_MAT2
25 B6 39 52 [6] I; PU
-
-
-
PIO0_16/AD5/
26 A6 40 53 [6] I; PU
CT32B1_MAT3/WAKEUP
I
I/O
I
O
I/O
I/O
I
O
I/O
PIO0_17/RTS/
CT32B0_CAP0/SCLK
-
-
30 A3 45 60 [3] I; PU
-
-
-
I
O
I/O
O
I
I/O
PIO0_18/RXD/
CT32B0_MAT0
31 B3 46 61 [3] I; PU I/O
-I
PIO0_19/TXD/
CT32B0_MAT1
-
32 B2 47 62 [3] I; PU
-
O
I/O
O
-
PIO0_20/CT16B1_CAP0 7 F2 9 11 [3] I; PU
-
PIO0_21/CT16B1_MAT0/ 12 G4 17 22 [3] I; PU
MOSI1
-
-
PIO0_22/AD6/
CT16B1_MAT1/MISO1
20 E8 30 40 [6] I; PU
-
-
-
O
I/O
I
I/O
O
I/O
I/O
I
O
I/O
TRST — Test Reset for JTAG interface.
PIO0_14 — General purpose digital input/output pin.
AD3 — A/D converter, input 3.
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO — Serial wire debug input/output.
PIO0_15 — General purpose digital input/output pin.
AD4 — A/D converter, input 4.
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO0_16 — General purpose digital input/output pin.
In Deep power-down mode, this pin functions as the
WAKEUP pin with 20 ns glitch filter. Pull this pin HIGH
externally to enter Deep power-down mode. Pull this
pin LOW to exit Deep power-down mode. A
LOW-going pulse as short as 50 ns wakes up the
part.
AD5 — A/D converter, input 5.
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
PIO0_17 — General purpose digital input/output pin.
RTS — Request To Send output for USART.
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
SCLK — Serial clock input/output for USART in
synchronous mode.
PIO0_18 — General purpose digital input/output pin.
RXD — Receiver input for USART. Used in UART ISP
mode.
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO0_19 — General purpose digital input/output pin.
TXD — Transmitter output for USART. Used in UART
ISP mode.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO0_20 — General purpose digital input/output pin.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO0_21 — General purpose digital input/output pin.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
MOSI1 — Master Out Slave In for SSP1.
PIO0_22 — General purpose digital input/output pin.
AD6 — A/D converter, input 6.
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
MISO1 — Master In Slave Out for SSP1.
LPC11U2X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.3 — 27 March 2014
© NXP B.V. 2014. All rights reserved.
11 of 74

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