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PDF CY7C109D Data sheet ( Hoja de datos )
| Número de pieza | CY7C109D | |
| Descripción | 1-Mbit (128 K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C109D
CY7C1009D
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
■ Pin- and function-compatible with CY7C109B/CY7C1009B
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 80 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 3 mA
■ 2.0 V Data Retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE1, CE2 and OE options
■ CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available in
Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description
The CY7C109D/CY7C1009D [1] is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1), an
active HIGH Chip Enable (CE2), an active LOW Output Enable
Logic Block Diagram
(OE), and tri-state drivers.The eight input and output pins (I/O0
through I/O7) are placed in a high-impedance state when:
■ Deselected (CE1 HIGH or CE2 LOW),
■ Outputs are disabled (OE HIGH),
■ When the write operation is active (CE1 LOW, CE2 HIGH, and
WE LOW)
Write to the device by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0 through
A16).
Read from the device by taking Chip Enable One (CE1) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE2) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the I/O pins.
The CY7C109D/CY7C1009D device is suitable for interfacing
with processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE1
CE2
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05468 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 16, 2015
1 page  
CY7C109D
CY7C1009D
Capacitance
Parameter [5]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [5]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
Max Unit
8 pF
8 pF
Test Conditions
Still Air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
300-Mil Wide
SOJ
57.61
400-Mil Wide
SOJ
56.29
40.53
38.14
TSOP I
50.72
16.21
Unit
°C/W
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [6]
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5 V
(a)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
10%
90%
10%
Rise Time: 3 ns
(b) Fall Time: 3 ns
High-Z characteristics:
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(c)
R2
255
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown
in Figure 3 (c).
Document Number: 38-05468 Rev. *J
Page 5 of 16
5 Page 
CY7C109D
CY7C1009D
Truth Table
CE1
CE2
OE
WE
I/O0–I/O7
Mode
Power
H X X X High Z
Power-down
Standby (ISB)
X L X X High Z
Power-down
Standby (ISB)
L H L H Data Out Read
Active (ICC)
L H X L Data In
Write
Active (ICC)
L H H H High Z
Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
10 CY7C109D-10VXI
CY7C109D-10ZXI
CY7C1009D-10VXI
Package
Diagram
Package Type
51-85033 32-pin SOJ (400 Mils) Pb-free
51-85056 32-pin TSOP (Type I) Pb-free
51-85041 32-pin SOJ (300 Mils) Pb-free
Please contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7 C 1 xx9 D - 10 X X I
Temperature Range:
I = Industrial
Pb-free
Package Type: X = V or Z
V = 32-pin SOJ
Z = 32-pin TSOP Type I
Speed: 10 ns
Process Technology: D = C9, 90 nm Technology
xx9 = 09 or 009 = (400 Mils / 300 Mils) 1-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Operating
Range
Industrial
Document Number: 38-05468 Rev. *J
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C109D.PDF ] | |
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