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PDF BU8254GUW Data sheet ( Hoja de datos )
| Número de pieza | BU8254GUW | |
| Descripción | 35bit LVDS Transmitter | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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LVDS Interface ICs
35bit LVDS Transmitter
35:5 Serializer
BU8254GUW
No.13057EBT10
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits
range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The
ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
1) 35bits data of parallel LVCMOS level inputs are converted to five channels of LVDS data stream.
2) 30bits of RGB data and 5bits of timing and control data(HSYNC,VSYNC,DE,CNTL1,CNTL2) are
transmitted up to 784Mbps effective rate per LVDS channel.
3) Support clock frequency from 8MHz up to 112MHz.
4) Support consumer video format including 480i, 480P, 720P and 1080i as well.
5) Clock edge selectable
6) Power down mode
7) Support spread spectrum clock generator.
8) Support reduced swing LVDS for low EMI.
9) 30bit LVDS receiver is recommended to use BU90R104.
●Applications
Flat Panel Display
●Precaution
■This chip is not designed to protect from radioactivity.
■The chip is made strictly for the specific application or equipment.
Then it is necessary that the unit is measured as need.
■This document may be used as strategic technical data which subjects to COCOM regulations.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
1/17
2013.06 - Rev.B
1 page  
BU8254GUW
●Pin Description
Technical Note
Table 1 : Pin Description
Pin Name
Pin No.
Type
Descriptions
TAP, TAN
A3,A2
LVDS OUT
TBP, TBN
A4,B3
LVDS OUT
TCP, TCN
B5,A5
LVDS OUT
LVDS data out.
TDP, TDN
B7,A7
LVDS OUT
TEP, TEN
B8,A8
LVDS OUT
TCLKP, TCLKN
B6,A6
LVDS OUT
LVDS clock out.
TA0～TA6
D3,D2,D4,E3,E2,D1,E5
IN
TB0～TB6
E1,F2,F1,F4,G1,G4,J2
IN
TC0～TC6
K2,K3,J4,K4,H5,K5,J6
IN
Pixel data inputs.
TD0～TD6 K6,K7,J8,K8,J9,H10,G10
IN
TE0～TE6
XRST
G7,F8,F9,F6,F10,E8,D7
E7
RS F3
RF
VDD
J7
F7,J3
IN
IN
IN
IN
Power
H : Normal operation,
L : Power down (all outputs are Hi-Z)
LVDS swing mode, VREF *1select.
RS
LVDS
Swing
VDD
0.6～1.4V
350mV
350mV
GND
200mV
*1 VREF is Input Reference Voltage.
Small Swing
Input Support
N/A
RS-VREF
N/A
Input clock triggering edge select.
H : Rising edge, L : Falling edge.
Power supply pins for LVCMOS inputs and digital core.
CLKIN
E10
IN Clock input.
GND
E4,E9,G3,G9,J5
Ground Ground pins for LVCMOS inputs and digital core.
LVDS VDD
B4
Power Power supply pins for LVDS outputs.
LVDS GND
C3,C4,C7
Ground Ground pins for LVDS outputs.
PLLVDD C9 Power Power supply pin for PLL core.
PLLGND
C10 Ground Ground pins for PLL core.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
5/17
2013.06 - Rev.B
5 Page 
BU8254GUW
●AC Timing
■AC Timing Diagrams
LVCMOS Input
LVCMOS Output
LVDS Output
Vdiff=(TAP)-(TAN)
TAP
TAN
LVDS Output Load
90%
CLKIN
10%
tTCIT
80%
RL Vdiff 20%
tLVT
Technical Note
90%
10%
tTCIT
80%
20%
tLVT
LVCMOS Input
CLKIN VDD/2
tTCH
tTCP
VDD/2
tTS
tTCL
tTH
VDD/2
Tx0-Tx6
VDD/2
VDD/2
TCLKP
TCLKN
tTCD
Fig.6 AC Timing Diagrams
RF=L
RF=H
VOC
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
11/17
2013.06 - Rev.B
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet BU8254GUW.PDF ] | |
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