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PDF SK70704 Data sheet ( Hoja de datos )
| Número de pieza | SK70704 | |
| Descripción | 784 Kbps HDSL Data Pump Chip Set | |
| Fabricantes | Intel | |
| Logotipo |  |
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SK70704/SK70706
784 Kbps HDSL Data Pump Chip Set
Datasheet
The HDSL Data Pump is a chip set consisting of the following two devices:
s SK70704 Analog Core Chip (ACC)
s SK70706 HDSL Digital Transceiver (HDX)
The HDSL Data Pump is a 2-wire transceiver which provides echo-cancelling and 2B1Q line
coding. It incorporates transmit pulse shaping, filtering, line drivers, receive equalization, timing
and data recovery to provide 784 kbps, clear-channel, “data pipe” transmission. The Data Pump
provides Near-End Cross-Talk (NEXT) performance in excess of that required over all ANSI
and ETSI test loops. Typical transmission range on 26 AWG (0.4 mm) cable exceeds 13 kft (4
km) in a noise-free environment or 9.5 kft (2.9 km) with ANSI-specified noise levels.
The Data Pump meets the requirements of Bellcore TA-NWT-001210, ANSI T1 Technical Report
No. 28-1994 and ETSI ETR-152. It provides one end of a single-channel HDSL transmission
system from the twisted pair interface back to the Data Pump/HDSL data interface. The Data
Pump can be used at either the HTU-R or the HTU-C end of the interface.
Applications
s T1 (2-pair) and fractional T1 transport
s N-channel digital pair-gain
Product Features
s Wireless base station to switch interface
s Campus and private networking
s Fully integrated, 2-chip set for interfacing
to 2-wire HDSL lines at 784 kbps
s Single +5 V power supply
s Integrated line drivers, filters and hybrid
circuits result in greatly reduced external
logic and simplified support circuitry
requirements
s Simple line interface circuitry, via
transformer coupling, to twisted pair line
s Internal ACC voltage reference
s Converts serial binary data to scrambled
2B1Q encoded data
s Self-contained activation/start-up state
machine for simplified single loop designs
s Programmable for either central office
(HTU-C) or remote site (HTU-R)
applications
s
s Compliant with:
s – Bellcore TA-NWT-001210
s – ANSI HDSL Technical Report No. 28-
1994
s – ETSI ETR-152 (1995)
s – ITU G.991.1
s Design allows for operation in either
Software Control or stand-alone Hardware
Control mode
s Typical power consumption is less than 1.0
W allowing remote power feeding for
repeater and
HTU-R equipment
s Input or Output Reference Clock of 12.544
MHz
s Digital representation of receive signal
level and noise margin values available for
SNR controlled activation
As of January 15, 2001, this document replaces the Level One document
SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set.
Order Number: 249192-001
January 2001
1 page  
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
(Figure 14 and Figure 15, Reference Y1)42
21 ACC Absolute Maximum Ratings ........................................................................45
22 ACC Recommended Operating Conditions.........................................................45
23 ACC DC Electrical Characteristics (Over Recommended Range) ......................45
24 ACC Transmitter Electrical Parameters (Over Recommended Range) ..............46
25 ACC Receiver Electrical Parameters (Over Recommended Range) ..................47
26 HDX Absolute Maximum Ratings ........................................................................48
27 HDX Recommended Operating Conditions.........................................................48
28 HDX DC Electrical Characteristics (Over Recommended Range) ......................49
29 HDX/HDSL Data Interface Timing Specifications (Figure 19) .............................51
30 HDX/Microprocessor Interface Timing Specifications (Figure 21 and Figure 22)51
31 General System and Hardware Mode Timing .....................................................52
Datasheet
5
5 Page 
784 Kbps HDSL Data Pump Chip Set — SK70704/SK70706
Table 2. SK70706 HDX Pin Assignments/Signal Descriptions (Continued)
Group
Pin #
Symbol
I/O4
Description
Receive Frame and Stuff Bit Indicator. Goes High for 18 consecutive ICLK
10
RFST
DO periods to indicate four stuffing bits (b4703 - 4706) and 14 frame bits (b1-14)
on RDATA.
13
REFCLK
DI1
DO
12.544 MHz HDSL Reference Clock. In HTU-C Mode, this clock generates
transmit and receive timing and must have ±32 ppm accuracy.
In HTU-R Mode, this output is derived by dividing CK25M by two.
Operation Mode Select. When HTU-C is High, the Data Pump operates in
16
HTU-C
DI HTU-C mode; when HTU-C is Low, the Data Pump operates in HTU-R mode.
Tied to internal pull-up device.
17
ICLK
DO
Bit Rate Clock. Nominally 784 kHz, REFCLK is the source of ICLK in HTU-C
Mode. CK25M is the source of ICLK in HTU-R Mode.
Loss of Sync Word Indicator. Normally Low in Active States, goes High to
30
LOSW
DO indicate receipt of six consecutive mismatched frame synch words. LOSW is
logic High in all states except Active States.
Receive HDSL Data Stream. Output data to HDSL framer at 784 kbps:HDSL
User Port
payload of Loop 1 or Loop 2 bytes plus the F-bits, eoc, crc, losd, febe, ps,
8
RDATA
DO bpv, hrp, indc/indr and uib bits, Sync bits for frame positions b1-14, Stuff bits
for frame positions b4703 - 4706. RDATA bits are forced high in all states
except the Active State.
Receive Frame Pulse. Low for one ICLK cycle during the last bit of the
7
RFP
DO current HDSL receive frame on RDATA, either b4702 or b4706. Period is within
one baud time of 6 ms.2 RFP is valid when LOSW transitions Low.
Transmit HDSL Data Stream. Input data from HDSL framer at
784 kbps:HDSL payload of Loop 1 or Loop 2 bytes plus the F-bits, eoc, crc,
11
TDATA
DI1
losd, febe, ps, bpv, hrp, indc/indr and uib bits, Sync bits for frame positions b1-
14, Stuff dummy bits; may be 1s or 0s. Tied to internal pull-up device. When
ACTIVE, the Data Pump is transparent and the HDSL framer must generate
the appropriate bits on TDATA as shown in Table 5.
Transmit Frame Pulse. Should be Low for one ICLK cycle the during last bit
of the current HDSL frame on TDATA, either b4702 or b4706. Period is within
12 TFP DI1 one baud time of 6 ms.2 If TFP is pulled Low and is Low again three ICLK
cycles later, RDATA, RFP, RFST, ICLK, CK6MEN, and LOSW go to tri-state.
Tied to internal pull-up device.
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/392 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
4. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
AI/O = Analog Input/Output; S = Supply.
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
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