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PDF PT7C433833 Data sheet ( Hoja de datos )
| Número de pieza | PT7C433833 | |
| Descripción | Real-time Clock Module | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PT7C433833
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Real-time Clock Module (I2C Bus)
Product Features
Using external 32.768kHz quartz crystal
Supports I2C-Bus's high speed mode (400 kHz)
Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
Programmable square wave output signal
56-byte, battery-backed, nonvolatile (NV) RAM for
data storage
Automatic power-fail detect and switch circuitry of
battery backup
UL Recognized: E348121
Product Description
The PT7C4338 serial real-time clock is a low-power
clock/calendar with a programmable square-wave output
and 56 bytes of nonvolatile RAM.
Address and data are transferred serially via a 2-wire,
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in either the
24-hour or 12-hour format with AM/PM indicator.
The PT7C4338 series have a built-in power sense circuit
that detects power failures and automatically switches to
the battery supply.
Table 1 shows the basic functions of PT7C4338. More
details are shown in section: overview of functions.
Table 1. Basic functions of PT7C4338
Item
Function
Source: Crystal: 32.768kHz
1 Oscillator Oscillator enable/disable
Oscillator fail detect
2 Time
Time display
12-hour
24-hour
Century bit
3 Alarm interrupt
4 Programmable square wave output (Hz)
5 RAM
6 Battery backup
12-07-0001
1
PT7C4338
-
-
1, 4.096k, 8.192k, 32.768k
568
PT0321-6 07/04/12
1 page  
PT7C433833
Real-time Clock Module (I2C Bus)
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(TA = -40℃ to +85℃) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ.
Max. Unit
SCL Clock Frequency
Fast mode
100
fSCL Standard mode
-
- 400
kHz
- 100
Bus Free Time Between STOP and
Fast mode
1.3
START condition
tBUF Standard mode 4.7
-
-
- μs
-
Hold Time (Repeated) START Condition
(Note 2)
tHD:STA
Fast mode
Standard mode
0.6
4.0
-
-
-
-
μs
LOW Period of SCL Clock
Fast mode
tLOW Standard mode
1.3
4.7
-
-
- μs
-
HIGH Period of SCL Clock
tHIGH
Fast mode
Standard mode
0.6
4.0
-
-
- μs
-
Setup Time of Repeated START
Condition
tSU:STA
Fast mode
Standard mode
0.6
4.7
-
-
- μs
-
Data Hold Time (Note 3, 4)
tHD:STA
Fast mode
Standard mode
0
0
- 0.9 μs
--
Data Setup Time (Note 5)
tSU:STA
Fast mode
Standard mode
100
250
-
-
-
ns
-
Rise Time of Both SDA and SCL Signals
(Note 6)
Fall Time of Both SDA and SCL Signals
(Note 6)
Setup Time for STOP Condition
tr
tf
tSU:STO
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
0.6
4.0
-
-
-
-
-
-
300
1000
300
300
-
-
ns
ns
μs
Capacitance Load for Each Bus Line
CB
Note 6
- - 400 pF
I/O Capacitance (SDA, SCL)
CI/O
Note 1
- - 10 pF
Oscillator Stop Flag (OSF) Delay
tOSF
Note 7
- 100 - ms
Note 1: Limits of full temperature are guaranteed by design not production test.
Note 2: After this period, the first clock pulse is generated.
Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 4: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 5: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr MAX + tSU:DAT = 1000 + 250 =
1250ns before the SCL line is released.
Note 6: CB------total capacitance of one bus line in pF.
Note 7: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ VCC ≤ VCC MAX and 1.3V ≤ VBAT ≤ 3.7V.
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PT0321-6 07/04/12
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Real-time Clock Module (I2C Bus)
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Days of the week Counter
The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond
to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
Addr.
Description
D7
D6
D5
D4
D3 D2 D1 D0
(hex)
03 Days of the week
0
0
0
(default)
0
0
0
0 0 W4 W2 W1
0 0 Undefined Undefined Undefined
Calendar Counter
The data format is BCD format.
Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
Description D7 D6 D5 D4 D3 D2 D1 D0
(hex)
04 Dates
(default)
0
0
D20 D10
D8
D4
D2
D1
0 0 Undefined Undefined Undefined Undefined Undefined Undefined
05 Months
(default)
0 0 0 M10 M8 M4 M2 M1
0 0 0 Undefined Undefined Undefined Undefined Undefined
06 Years
Y80 Y40 Y20 Y10
Y8
Y4
Y2
Y1
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
12-07-0001
PT0321-6 07/04/12
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet PT7C433833.PDF ] | |
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