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74LS74 даташитФункция этой детали – «Dual D-type Positive Edge-triggered Flip-flops(with Preset And Clear)». |
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Номер в каталоге | Производители | Описание | |
74LS74 | ON Semiconductor |
LOW POWER SCHOTTKY SN74LS74A Dual D-Type Positive Edge-Triggered Flip-Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock in |
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74LS74 | National Semiconductor |
Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs 54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs
June 1989
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directl |
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74LS74 | Motorola Semiconductors |
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the |
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74LS74 | Hitachi Semiconductor |
Dual D-type Positive Edge-triggered Flip-Flops(With Preset and Clear) Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.10
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-14 Conforms Conforms 0.97 g
Unit: mm
10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8°
+ 0.20
1.42 Max
1.27 *0.42 ± 0.08 0.40 ± 0.06
0.10 ± 0.10
0.70 ± 0.20
0.15 0.12 M
Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g
*Dimens |
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74LS74 | Fairchild Semiconductor |
Dual Positive-Edge-Triggered D Flip-Flops DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
August 1986 Revised March 2000
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related |
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74LS74A | Texas Instruments |
Dual D-Type Positive-Edge -Triggered Flip-Flops With Preset And Clear |
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Последние обновления
Номер в каталоге | Производители | Описание | |
2N3904 | Unisonic Technologies |
Это популярный биполярный переходной транзистор (BJT), обычно используемый в электронных схемах. Транзистор NPN с максимальным номинальным током 200 мА и максимальным номинальным напряжением 40 В. |
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NE555 | ST Microelectronics |
Это широко используемая интегральная схема таймера (ИС), которую можно использовать для генерирования сигналов с точной временной задержкой, колебаний и широтно-импульсной модуляции (ШИМ). |
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