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74LS244 даташитФункция этой детали – «Octal Buffers / Line Drivers / Line Receivers». |
The 74LS244 is an octal buffer/line driver integrated circuit chip that is designed to provide high-speed signal buffering and amplification. |
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Номер в каталоге | Производители | Описание | |
74LS244 | ON Semiconductor |
Octal Buffers and Line
Drivers SN74LS240 SN74LS244 Octal Buffer/Line Driver with 3-State Outputs
The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.
http://onsemi.com
• Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address • Input Clamp Diodes Limit High-Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH Parameter Supp |
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74LS244 | Mitsubishi Electric Semiconductor |
OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUT(NONINVERTED) |
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74LS244 | Hitachi Semiconductor |
Octal Buffers / Line Drivers / Line Receivers (non inverted three-state outputs) Unit: mm
24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89
1.27 Max
10 1.30 2.54 Min 5.08 Max 7.62
0.51 Min
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.11
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-20N — Conforms 1.26 g
Unit: mm
12.6 13 Max
20
11
1
10
5.5
0.80 Max
2.20 Max
*0.22 ± 0.05 0.20 ± 0.04
0.20 7.80 + – 0.30
1.15
1.27 *0.42 ± 0.08 0.40 ± 0.06
0.10 ± 0.10
0° – 8°
0.70 ± 0.20
0.15
0.12 M
*Dimension including the plating thickness Base material dimension
Hitachi |
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74LS244 | Fairchild Semiconductor |
Octal 3-STATE Buffer/Line Driver/Line Receiver DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986 Revised March 2000
DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be |
Последние обновления
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2N3904 | Unisonic Technologies |
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|
NE555 | ST Microelectronics |
Это широко используемая интегральная схема таймера (ИС), которую можно использовать для генерирования сигналов с точной временной задержкой, колебаний и широтно-импульсной модуляции (ШИМ). |
DataSheet26.com | 2020 | Контакты |