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74F109 даташит

Функция этой детали – «Dual Jk (note: Overbar Over The K) Positive».



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Номер в каталоге Производители Описание PDF
74F109 Texas Instruments
Texas Instruments
  Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop (Rev. A)

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74F109 NXP Semiconductors
NXP Semiconductors
  Positive J-K positive edge-triggered flip-flops

INTEGRATED CIRCUITS 74F109 Positive J-K positive edge-triggered flip-flops Product specification IC15 Data Handbook 1990 Oct 23 Philips Semiconductors Philips Semiconductors Product specification Postive J-K positive edge-triggered flip-flops 74F109 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) ar
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74F109 Fairchild Semiconductor
Fairchild Semiconductor
  Dual JK Positive Edge-Triggered Flip-Flop

74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q
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74F109PC National Semiconductor
National Semiconductor
  Dual JK Positive Edge-Triggered Flip-Flop

54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop 54F/74F109 November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets
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74F109PC Fairchild Semiconductor
Fairchild Semiconductor
  Dual JK Positive Edge-Triggered Flip-Flop

74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q
pdf
74F109SC National Semiconductor
National Semiconductor
  Dual JK Positive Edge-Triggered Flip-Flop

54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop 54F/74F109 November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets
pdf
74F109SC Fairchild Semiconductor
Fairchild Semiconductor
  Dual JK Positive Edge-Triggered Flip-Flop

74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q
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74F109SJ National Semiconductor
National Semiconductor
  Dual JK Positive Edge-Triggered Flip-Flop

54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop 54F/74F109 November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets
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Последние обновления

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Номер в каталоге Производители Описание PDF
2N3904 Unisonic Technologies
Unisonic Technologies

Это популярный биполярный переходной транзистор (BJT), обычно используемый в электронных схемах. Транзистор NPN с максимальным номинальным током 200 мА и максимальным номинальным напряжением 40 В.

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NE555 ST Microelectronics
ST Microelectronics

Это широко используемая интегральная схема таймера (ИС), которую можно использовать для генерирования сигналов с точной временной задержкой, колебаний и широтно-импульсной модуляции (ШИМ).

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