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PDF LTC6268 Data sheet ( Hoja de datos )
| Número de pieza | LTC6268 | |
| Descripción | 500MHz Ultra-Low Bias Current FET Input Op Amp | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTC6268/LTC6269
500MHz Ultra-Low Bias
Current FET Input Op Amp
FEATURES
n Gain Bandwidth Product: 500MHz
n –3dB Bandwidth (A = 1): 350MHz
n Low Input Bias Current:
±3fA Typ. Room Temperature
4pA Max at 125°C
n Current Noise (100kHz): 5.5fA/√Hz
n Voltage Noise (1MHz): 4.3nV/√Hz
n Extremely Low CIN 450fF
n Rail-to-Rail Output
n Slew Rate: 400V/µs
n Supply Range: 3.1V to 5.25V
n Quiescent Current: 16.5mA
n Harmonic Distortion (2VP-P):
–100dB at 1MHz
–80dB at 10MHz
n Operating Temp Range: –40°C to 125°C
n Single in 8-Lead SO-8, 6-Lead TSOT-23 Packages
n Dualin8-LeadMS8,3mm × 3mm10-LeadDFN10 Packages
APPLICATIONS
n Trans-Impedance Amplifiers
n ADC Drivers
n CCD Output Buffer
n Photomultiplier Tube Post-Amplifier
n Low IBIAS Circuits
DESCRIPTION
The LTC®6268/LTC6269 is a single/dual 500MHz FET-input
operational amplifier with extremely low input bias current
and low input capacitance. It also features low input-
referred current noise and voltage noise making it an ideal
choice for high speed transimpedance amplifiers, CCD
output buffers, and high-impedance sensor amplifiers.
Its low distortion makes the LTC6268/LTC6269 an ideal
amplifier for driving SAR ADCs.
It operates on 3.1V to 5.25V supply and consumes 16.5mA
per amplifier. A shutdown feature can be used to lower
power consumption when the amplifier is not in use.
The LTC6268 single op amp is available in 8-lead SOIC and
6-lead SOT-23 packages. The SOIC package includes two
unconnected pins which can be used to create an input pin
guard ring to protect against board leakage currents. The
LTC6269 dual op amp is available in 8-lead MSOP with
exposed pad and 3mm × 3mm 10-lead DFN packages.
They are fully specified over the –40°C to 85°C and the
–40°C to 125°C temperature ranges.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
20kΩ Gain 65MHz Trans-Impedance Amplifier
2.5V
PD
IPD
20kΩ*
2.5V
–
LTC6268
+
PARASITIC
FEEDBACK C
VOUT = –IPD • 20k
BW = 65MHz
–2.5V
6268 TA01
PD = OSI OPTOELECTRONICS, FCI-125G-006
*TWO 40.2kΩ 0603 PACKAGE RESISTORS IN PARALLEL
20kΩ TIA Frequency Response
100
90
80
70
60
50
40
0.01
0.1 1 10 100 1000
FREQUENCY (MHz)
6268 TA02
For more information www.linear.com/LTC6268
62689f
1
1 page  
LTC6268/LTC6269
3 .3V ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply), RL = 1kΩ,
CL = 10pF, VSHDN is unconnected.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VOS Input Offset Voltage
VCM = 1.0V
–0.7
l –2.5
0.2
0.7
2.5
mV
mV
VCM = 2.3V
–1.0
l –4.5
0.2
1.0
4.5
mV
mV
TC VOS Input Offset Voltage Drift
IB Input Bias Current (Notes 6, 8)
VCM = 1.0V
VCM = 1.0V
LTC6268I/LTC6269I
LTC6268H/LTC6269H
4
–20 ±3
20
l –900
900
l –4
4
µV/C
fA
fA
pA
VCM = 2.3V
–20 ±3
LTC6268I/LTC6269I l –900
LTC6268H/LTC6269H
l –4
20
900
4
fA
fA
pA
IOS Input Offset Current (Notes 6, 8)
VLTCCM6=2618.0I/VLTC6269I l ––44500 ±6
LTC6268H/LTC6269H
l –2
40
450
2
fA
fA
pA
en Input Voltage Noise Density, VCM =1.0V f = 1MHz
Input Voltage Noise Density, VCM = 2.3V f = 1MHz
Input Referred Noise Voltage
f = 0.1Hz to 10Hz
in Input Current Noise Density, VCM = 1.0V f = 100kHz
Input Current Noise Density, VCM = 2.3V f = 100kHz
RIN Input Resistance
Differential
Common Mode
4.3
4.9
13
5.6
5.3
>1000
>1000
nV/√Hz
nV/√Hz
μVP-P
fA/√Hz
fA/√Hz
GΩ
GΩ
CIN Input Capacitance
Differential (DC to 200MHz)
Common Mode (DC to 100MHz)
100 fF
450 fF
CMRR Common Mode Rejection Ratio
VCM = 0.5V to 1.2V (PNP Side)
63
l 60
100
dB
dB
VCM = 0V to 2.8V (Full Range)
60
l 50
77
dB
dB
IVR Input Voltage Range
Guaranteed by CMRR
l0
2.8 V
AV Open Loop Voltage Gain
VOUT = 0.5V to 2.8V
RLOAD = 10k
80
l 40
200
V/mV
V/mV
RLOAD = 100
10
l2
18
V/mV
V/mV
VOL Output Swing Low
(Input Overdrive 30mV).
Measured from V–
ISINK = 10mA
ISINK = 25mA
80 140
mV
l 200 mV
140 200
mV
l 260 mV
VOH Output Swing High
(Input Overdrive 30mV).
Measured from V+
ISOURCE = 10mA
ISOURCE = 25mA
80 140
mV
l 200 mV
170 270
mV
l 370 mV
ISC Output Short Circuit Current
(Note 9)
50
l 35
80
mA
mA
IS Supply Current per Amplifier
14.5 16 17.5
l9
23
mA
mA
For more information www.linear.com/LTC6268
62689f
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5 Page 
LTC6268/LTC6269
PIN FUNCTIONS
–IN: Inverting Input of the Amplifier. The voltage range of
this pin is from V– to V+ –0.5V.
+IN: Non-Inverting Input. The voltage range of this pin is
from V– to V+ –0.5V.
V+: Positive Power Supply. Total supply (V+ – V–) voltage
is from 3.1V to 5.25V. Split supplies are possible as long
as the total voltage between V+ and V– is between 3.1V and
5.25. A bypass capacitor of 0.1µF should be used between
V+ to ground as close to the pin as possible.
V–: Negative Power Supply. Normally tied to ground, it
can also be tied to a voltage other than ground as long
as the voltage difference between V+ and V– is between
3.1V and 5.25V. If it is not connected to ground, bypass
it to ground with a capacitor of 0.1µF as close to the pin
as possible.
SHDN, SDA, SDB: Active Low op amp shutdown, threshold
is 0.75V above the negative supply, V–. If left unconnected,
the amplifier is enabled.
OUT: Amplifier Output.
NC: Not connected. May be used to create a guard ring
around the input to guard against board leakage currents.
See Applications Information section for more details.
SIMPLIFIED SCHEMATIC
V+
ESD_D2
INPUT REPLICA
ESD_D0
+IN
–IN
CMOS INPUT
BUFFER
ESD_D1
D6
INPUT REPLICA
ESD_D3
SD
D7
V–
COMPLEMENTARY
I0 INPUT STAGE
Q3 Q9 Q4
Q5 Q6
Q7 Q8
REFERENCE
GENERATION
LTC6268 Simplified Schematic Diagram
C0
BUFFER
Q1
D4
OUT
Q2 D5
6268 BD
For more information www.linear.com/LTC6268
62689f
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC6268.PDF ] | |
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