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PDF LTM2220-AA Data sheet ( Hoja de datos )
| Número de pieza | LTM2220-AA | |
| Descripción | 170Msps ADC | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTM2220-AA
12-Bit, 170Msps ADC
FEATURES
■ Pin Compatible with the AD9430
■ Sample Rate: 170Msps
■ 66.2dB SNR, 84dB SFDR
■ No Missing Codes
■ Single 3.3V supply
■ Power Dissipation: 1050mW
■ LVDS Digital Outputs
■ 1.536VPP Input Range
■ Clock Duty Cycle Stabilizer
■ Out-of-Range Indicator
■ Data Ready Output Clock
■ Integrated Bypass Capacitors
■ 100-Pin SiPLGA Package
APPLICATIONS
■ Wireless and Wired Broadband Communication
■ Spectral Analysis
DESCRIPTION
The LTM®2220-AA is a 170Msps sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTM2220-AA is perfect for
demanding communications applications with AC per-
formance that includes 66.2dB SNR and 84dB spurious
free dynamic range.
DC specs include ±0.5LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature.
The CLK+ and CLK- inputs may be driven differentially or
single ended with a sine wave, PECL, TTL or CMOS inputs.
A clock duty cycle stabilizer allows high performance at
full speed for a wide range of clock duty cycles.
The LTM2220-AA is pin compatible with the AD9430 when
used with LVDS outputs, 2’s complement output format
and the 1.536VPP input range.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT
REFERENCE
+
INPUT
S/H
–
CLOCK/DUTY
CYCLE
CONTROL
CLOCK
INPUT
3.3V
AVDD
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
3.3V
DRVDD
D11
•
•
•
LVDS
OUTPUTS
D0
DRGND
AGND
2220 TA01
2220aaf
1
1 page  
LTM2220-AA
TYPICAL PERFORMANCE CHARACTERISTICS
8192 Point FFT, fIN = 5MHz, –1dB,
170Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2220 G01
8192 Point FFT, fIN = 140MHz,
–1dB, 170Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2220 G04
8192 Point FFT, fIN = 30MHz,
–1dB, 170Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2220 G02
INL Error
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
0
1024
2048
3072
OUTPUT CODE
4096
2220 G05
8192 Point FFT, fIN = 70MHz,
–1dB, 170Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2220 G03
DNL Error
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
0
1024
2048
3072
OUTPUT CODE
4096
2220 G06
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5
5 Page 
PACKAGE DESCRIPTION
SiPLGA Package
100-Lead (16mm × 16mm)
(Reference LTC DWG # 05-08-1802 Rev Ø)
LTM2220-AA
aaa Z
15.90 – 16.10
X
26 50 (2X)
Y
6.000
5.500
5.000
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
0.500
1.000
1.500
2.000
2.500
3.000
3.500
4.000
4.500
5.000
5.500
6.000
25
1
3.1245
1.045
1.045
3.1245
3.1245
1.045
1.045
3.1245
100 DETAILED PAD LAYOUT
76
PAD 1
51 4 CORNER
75
15.9 – 16.1
TOP VIEW
aaa Z
(2X)
0.315 – 0.385
0.218 – 0.278 (b)
1.120 – 1.180
PAD 1.313 – 1.383
DETAIL B
1.93 – 2.13
eee M X Y
0.05 – 0.15
25
26
0.5
BASIC
11.90 – 12.10
11.90 – 12.10
50
SUBSTRATE
MOLD
CAP
0.33 – 0.43
5
1.60 – 1.70
DETAIL B
1
DETAIL A
DETAIL A
100 76
COLUMNS 1
3 5 7 9 11 13 15 17 19 21 23 25
2 4 6 8 10 12 14 16 18 20 22 24 26
BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
3 LAND DESIGNATION PER JESD MO-222, SPP-010
4 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD
OR MARKED FEATURE
5 PRIMARY DATUM -Z- IS SEATING PLANE
6. DIMENSION (b) IS MEASURED AT THE MAXIMUM LAND
WIDTH, PARALLEL TO PRIMARY DATUM -Z-
SYMBOL TOLERANCE
aaa 0.10
bbb 0.10
eee 0.03
10_10_06
7. TOTAL NUMBER OF PADS: 104 TOTAL (100 PERIPHERAL + 4 COMMON CENTER)
ROWS
AF
51 AE
AD
AC
AB
AA
Y
W
V
U
T
S
R
P
N
M
L
K
J
H
G
F
E
D
C
75 B
A
3
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTM2220-AA.PDF ] | |
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