|
|
PDF TH58NVG7T2ELA46 Data sheet ( Hoja de datos )
| Número de pieza | TH58NVG7T2ELA46 | |
| Descripción | 128 GBIT (4G x 8 BIT x 4) CMOS NAND E2PROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TH58NVG7T2ELA46 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
TOSHIBA CONFIDENTIAL TH58NVG7T2ELA46
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128 GBIT (4G × 8 BIT x 4) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TH58NVG7T2E is a single 3.3 V 128 Gbit (145,572,102,144bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 192 pages × 2780 blocks × 4.
The device has two 8568-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 8568-byte increments. The Erase operation is implemented in a single block
unit (1536 Kbytes + 70.5 Kbytes:8568 bytes x 192 pages).
The TH58NVG7T2E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell array
Register
Page size
Block size
TH58NVG7T2E
8568 × 521.3K × 8 x 4
8568 × 8
8568 bytes
(1536K + 70.5K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase,Multi Page Copy, Mullti Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 10624 blocks
Max 11120 blocks
• Power supply
VCC = 2.7 V to 3.6 V
VCCQ = 2.7 V to 3.6 V
• Access time
Cell array to register 250 µs max
Serial Read Cycle
25 ns min
• Program/Erase time
Auto Page Program
Auto Block Erase
2700 µs/page typ.
4 ms/block typ.
• Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
60 mA max. (per 1chip)
60 mA max. (per 1chip)
60 mA max. (per 1chip)
400 µA max
• Package
P – TLGA40 – 1317 – 1.04AZ (Weight: 0.46g typ.)
• FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).
24 bit ECC for each 1K bytes is required.
1 2009-07-14C
1 page  
TOSHIBA CONFIDENTIAL TH58NVG7T2ELA46
VALID BLOCKS*
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NVB Number of Valid Blocks
10624
⎯
11120
Blocks
NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over the device lifetime.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
VCC Power Supply Voltage
2.7 V
⎯ 3.6 V
V
VIH
High Level input Voltage
2.7 V ≤ VCC ≤ 3.6 V
0.8 x Vcc
⎯ VCC + 0.3
V
VIL Low Level Input Voltage
* −2 V (pulse width lower than 20 ns)
2.7 V ≤ VCC ≤ 3.6 V
−0.3*
⎯ 0.2 x Vcc
V
DC CHARACTERISTICS (Ta = 0 to 70°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
CONDITION
IIL Input Leakage Current
ILO Output Leakage Current
ICCO0 *1, *2 Power On Reset Current
ICCO1 *2
ICCO2 *2
ICCO3 *2
ICCS
Serial Read Current
Programming Current
Erasing Current
Standby Current
VIN = 0 V to VCC
VOUT = 0 V to VCCQ
PSL = GND or NU
PSL = Vcc,FFh command input after
Power On
CE = VIL, IOUT = 0 mA, tcycle = 50 ns
⎯
⎯
CE = VCC − 0.2 V, WP = 0 V/VCC,
PSL=0V/Vcc/NU
MIN
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
VOH
High Level Output Voltage IOH = −0.4 mA (2.7 V ≤ VCC ≤ 3.6 V)
2.4
TYP.
⎯
⎯
⎯
⎯
⎯
⎯
—
⎯
⎯
VOL
Low Level Output Voltage IOL = 2.1 mA (2.7 V ≤ VCC ≤ 3.6 V)
⎯⎯
IOL
( RY / BY )
Output current of RY / BY
pin
VOL = 0.4 V (2.7 V ≤ VCC ≤ 3.6 V)
⎯
*1 Refer to application note(2) for detail
*2 Icco0/1/2/3 are the value of one chip, and an unselected chip is in Standy mode.
8
MAX
±10
±10
60
60
60
60
60
400
⎯
0.4
⎯
UNIT
µA
µA
mA
mA
mA
mA
mA
µA
V
V
mA
5 2009-07-14C
5 Page 
TOSHIBA CONFIDENTIAL TH58NVG7T2ELA46
Read Cycle Timing Diagram
CLE
CE
tCLS
tCS
tCLH
tCH
tWC
tCLS tCLH
tCS tCH
tCLR
tCR
WE
tALH tALS
tALH tALS
ALE
RE
I/O
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0 CA8 PA0 PA8 PA16
to 7 to 13 to 7 to 15 to 20
Col. Add. N
tR
tWB
tDS tDH
30h
tRC
tRR tREA
DOUT DOUT
N N+1
Data out from
Col. Add. N
Read Cycle Timing Diagram: When Interrupted by CE
CLE
CE
tCLS
tCS
tCLH
tCH
tWC
WE
tALH tALS
tCLS tCLH
tCS tCH
tALH tALS
ALE
RE
I/O
RY / BY
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0 CA8 PA0 PA8 PA16
to 7 to 13 to 7 to 15 to 20
Col. Add. N
tR
tWB
tDS tDH
30h
tCLR
tCR
tCHZ
tRC tRHZ
tRR tREA tRHOH
DOUT DOUT
N N+1
Col. Add. N
11 2009-07-14C
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TH58NVG7T2ELA46.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TH58NVG7T2ELA46 | 128 GBIT (4G x 8 BIT x 4) CMOS NAND E2PROM | Toshiba |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |