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PDF STM32F101RG Data sheet ( Hoja de datos )
| Número de pieza | STM32F101RG | |
| Descripción | 32-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM32F101xF
STM32F101xG
XL-density access line, ARM®-based 32-bit MCU with 768 KB
to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces
Datasheet − production data
Features
• Core: ARM® 32-bit Cortex®-M3 CPU with MPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance
– Single-cycle multiplication and hardware
division
• Memories
– 768 Kbytes to 1 Mbyte of Flash memory
(dual bank with read-while-write capability)
– 80 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND
memories
– LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
capability
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• 1 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
• 2 × 12-bit D/A converters
• DMA
– 12-channel DMA controller
– Peripherals supported: timers, ADC, DAC,
SPIs, I2Cs and USARTs
• Up to 112 fast I/O ports
LQFP144
20 × 20 mm
LQFP100
14 × 14 mm
LQFP64
10 × 10 mm
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
• Debug mode
– Serial wire debug (SWD) & JTAG
interfaces
– Cortex-M3 Embedded Trace Macrocell™
• Up to 15 timers
– Up to ten 16-bit timers, with up to 4
IC/OC/PWM or pulse counters
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
• Up to 10 communication interfaces
– Up to 2 x I2C interfaces (SM7816 interface,
LIN, IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s)
• CRC calculation unit, 96-bit unique ID
• ECOPACK® packages
Table 1. Device summary
Reference
Part number
STM32F101xF
STM32F101RF STM32F101VF
STM32F101ZF
STM32F101xG
STM32F101RG STM32F101VG
STM32F101ZG
May 2015
This is information on a product in full production.
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STM32F101xF, STM32F101xG
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F101xF and STM32F101xG features and peripheral counts . . . . . . . . . . . . . . . . . 11
STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F101xF and STM32F101xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19
STM32F101xF/STM32F101xG pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 44
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 47
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59
Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Switching characteristics for PC Card/CF read and write cycles in
attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 74
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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STM32F101xF, STM32F101xG
Description
2.1
Device overview
The STM32F101xx XL-density access line family offers devices in 3 different package
types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
Figure 1 shows the general block diagram of the device family.
Table 2. STM32F101xF and STM32F101xG features and peripheral counts
Peripherals
STM32F101Rx
STM32F101Vx
STM32F101Zx
Flash memory
SRAM in Kbytes
FSMC
Timers
General-purpose
Basic
Communication
interfaces
SPI
I2C
USART
GPIOs
12-bit ADC
Number of channels
12-bit DAC
Number of channels
CPU frequency
Operating voltage
Operating temperatures
Package
768 KB 1 MB 768 KB 1 MB 768 KB 1 MB
80 80 80
No Yes Yes
10
2
3
2
5
51 80 112
1
16
YES
2
36 MHz
2.0 to 3.6 V
Ambient temperature: –40 to +85 °C (see Table 10)
Junction temperature: –40 to +105 °C (see Table 10)
LQFP64
LQFP100(1)
LQFP144
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a
multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND
Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available
in this package.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STM32F101RG.PDF ] | |
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