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PDF AT86RF231-ZU Data sheet ( Hoja de datos )
| Número de pieza | AT86RF231-ZU | |
| Descripción | Low Power 2.4 GHz Transceiver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4™,
ZigBee®, 6LoWPAN, RF4CE, SP100, WirelessHART™ and ISM Applications
• Industry Leading Link Budget (104 dB)
– Receiver Sensitivity -101 dBm
– Programmable Output Power from -17 dBm up to +3 dBm
• Ultra-Low Current Consumption:
– SLEEP
= 0.02 µA
– TRX_OFF
= 0.4 mA
– RX_ON
= 12.3 mA
– BUSY_TX
= 14 mA (at max. Transmit Power of +3 dBm)
• Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator
• Optimized for Low BoM Cost and Ease of Production:
– Few External Components Necessary (Crystal, Capacitors and Antenna)
– Excellent ESD Robustness
• Easy to Use Interface:
– Registers, Frame Buffer and AES Accessible through Fast SPI
– Only Two Microcontroller GPIO Lines Necessary
– One Interrupt Pin from Radio Transceiver
– Clock Output with Prescaler from Radio Transceiver
• Radio Transceiver Features:
– 128-byte FIFO (SRAM) for Data Buffering
– Programmable Clock Output, to Clock the Host Microcontroller or as Timer
Reference
– Integrated RX/TX Switch
– Fully Integrated, Fast Settling PLL to support Frequency Hopping
– Battery Monitor
– Fast Wake-Up Time < 0.4 msec
• Special IEEE 802.15.4-2006 Hardware Support:
– FCS Computation and Clear Channel Assessment
– RSSI Measurement, Energy Detection and Link Quality Indication
• MAC Hardware Accelerator:
– Automated Acknowledgement, CSMA-CA and Retransmission
– Automatic Address Filtering
– Automated FCS Check
• Extended Feature Set Hardware Support:
– AES 128-bit Hardware Accelerator
– RX/TX Indication (external RF Front-End Control)
– RX Antenna Diversity
– Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s
– True Random Number Generation for Security Application
• Industrial and Extended Temperature Range:
– -40°C to +85°C and -40°C to +125°C
• I/O and Packages:
– 32-pin Low-Profile QFN Package 5 x 5 x 0.9 mm³
– RoHS/Fully Green
• Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003
• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-T66, RSS-210
Low Power
2.4 GHz
Transceiver for
ZigBee,
IEEE 802.15.4,
6LoWPAN,
RF4CE, SP100,
WirelessHART,
and ISM
Applications
AT86RF231-ZU
AT86RF231-ZF
8111C–MCU Wireless–09/09
1 page  
AT86RF231
1.2 Analog and RF Pins
1.2.1
Supply and Ground Pins
EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio
transceiver.
AVDD, DVDD
AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are
controlled independently by the radio transceivers state machine and are activated dependent
on the current radio transceiver state. The voltage regulators can be configured for external
supply.
For details, refer to Section 9.4 “Voltage Regulators (AVREG, DVREG)” on page 110.
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power
domains should be separated on the PCB.
1.2.2 RF Pins
RFN, RFP
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching
noise of the internal digital signal processing blocks. At board-level, the differential RF layout
ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital
ICs such as a microcontroller.
A simplified schematic of the RF front end is shown in Figure 1-2 on page 5.
Figure 1-2. Simplified RF Front-end Schematic
PCB AT86RF231
LNA RX
RFP
RFN
PA TX
0.9V
CM
Feedback
M0 RXTX
The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed.
A DC path to ground or supply voltage is not allowed. Therefore, when connecting an RF-load
providing a DC path to the power supply or ground, AC-coupling is required as indicated in Table
1-2 on page 6.
8111C–MCU Wireless–09/09
5
5 Page 
AT86RF231
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the
received data.
The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the
SPI interface and additional control lines.
The AT86RF231 further contains comprehensive hardware-MAC support (Extended Operating
Mode) and a security engine (AES) to improve the overall system power efficiency and timing.
The stand-alone 128-bit AES engine can be accessed in parallel to all PHY operational transac-
tions and states using the SPI interface, except during SLEEP state.
For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radio trans-
ceiver also supports alternative data rates up to 2 Mb/s.
For long-range applications or to improve the reliability of an RF connection the RF performance
can further be improved by using an external RF front-end or Antenna Diversity. Both operation
modes are supported by the AT86RF231 with dedicated control pins without the interaction of
the microcontroller.
Additional features of the Extended Feature Set, see Section 11. “AT86RF231 Extended Fea-
ture Set” on page 128, are provided to simplify the interaction between radio transceiver and
microcontroller.
8111C–MCU Wireless–09/09
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT86RF231-ZU.PDF ] | |
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