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PDF 82C547 Data sheet ( Hoja de datos )

Número de pieza 82C547
Descripción PYTHON CHIPSET FOR PENTIUM PROCESSORS
Fabricantes OPTi　
Logotipo OPTi Logotipo



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No Preview Available ! 82C547 Hoja de datos, Descripción, Manual

PYTHON CHIPSET
FOR PENTIUM ™
PROCESSORS
May 1994
OPTi Inc.. 2525 Walsh Avenue· Santa Clara, CA 95051 . (408) 980-8178

1 page




82C547 pdf
Table of Contents
82C546/82C547
1.0 Features .............................................................................................................................................1
2.0 Overview ...........................................................................................................................................2
2.1 82C546 (ATC) AT Bus Controller ....•.......................................•............................................................•.....•..... 2
2.2 82C547 (SYSC) System Controller .................................................................................................................... 2
2.3 82C206 (IPC) Integrated Peripheral Controller.......................•....•..................................•............................... 3
2.4 Support Chips ...................................................................................................................................................... 3
3.0 Signal Definitions..............................................................................................................................5
3.1 Signal Descriptions .........•...................................................•............•.•.................•............................................• 17
3.1.1
82C546 ATC Signal Descriptions ....................................................................................................... 17
3.1.1.1 Clock and Reset Interface Signals ...................................................................................... 17
3.1.1.2 Data Bus Interface Signals.................................................................................................. 17
3.1.1.3 Local Bus Interface Signals ................................................................................................ 18
3.1.1.4 Buffer Control Interface Signals......................................................................................... 19
3.1.1.5 Bus Arbitration Interface Signals ....................................................................................... 20
3.1.1.6 AT Bus Interface Signals .................................................................................................... 20
3.1.1.7 Miscellaneous Interface Signals ......................................................................................... 21
3.1.1.8 Power and Ground Pins ...................................................................................................... 21
3.1.2
82C547 SYSC Signal Descriptions ..................................................................................................... 22
3.1.2.1 Clock and Reset Interface Signals ...................................................................................... 22
3.1.2.2 Data Bus Interface Signals.................................................................................................. 22
3.1.2.3 VL Bus Interface Signals .................................................................................................... 23
3.1.2.4 Cache Interface Signals ...................................................................................................... 24
3.1.2.5 System DRAM Interface Signals........................................................................................ 25
3.1.2.6 Bus Arbitration Interface Signals ....................................................................................... 25
3.1.2.7 Data Buffer Interface Signals ............................................................................................. 26
3.1.2.8 Miscellaneous Interface Signals ......................................................................................... 26
3.1.2.9 Ground and Power Pins ...................................................................................................... 27
3.1.3
3.1.4
82C606A Signal Descriptions.............................................................................................................. 28
3.1.3.1 CPU Interface Signals......................................................................................................... 28
3.1.3.2 ISANLlMemory Bus Interface Signals ............................................................................. 28
3.1.3.3 Buffer Control Interface Signals......................................................................................... 28
3.1.3.4 Ground and Power Pins ...................................................................................................... 29
-
82C606B Signal Definitions ................................................................................................................ 30
3.1.4.1 CPU/Cache Interface Signals ............................................................................................. 30
3.1.4.2 ISANL Bus Interface Signals ............................................................................................ 30
Python Chipset
DBS-Ol·CS002-1.0
Page iii

5 Page





82C547 arduino
List of Tables
82C546/82C547
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 4-7
Table 4-8
Table 4-9
Table 4-10
Table 4-11
Table 4-12
Table 4-13
Table 4-14
Table 4-15
Table 4-16
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table 5-8
82C546 ATC Numerical Pin Cross-Reference List ...................................................................................... 6
82C546 ATC Alphabetical Pin Cross-Reference List .................................................................................. 7
82C547 SYSC Numerical Pin Cross-Reference List ..........................,......................................................... 9
82C547 SYSC Alphabetical Pin Cross-Reference...................................................................................... 10
82C606A Numerical Pin Cross-Reference ................................................................................................. 12
82C606A Alphabetical Pin Cross-Reference.............................................................................................. 13
82C606B Numerical Pin Cross-Reference.................................................................................................. 15
82C606B Alphabetical Pin Cross-Reference .............................................................................................. 16
Power-On Reset and LCK Relationship ..................................................................................................... 34
Power-On Reset and LCLK to ATCLK Relationship................................................................................. 35
Power-On Reset and 110 Buffer Select ....................................................................................................... 36
Tag Compare ............................................................................................................................................... 44
DMAlMaster Read Cycle Summary ........................................................................................................... 46
DMAlMaster Write Cycle Summary .......................................................................................................... 49
Write Protection Control Methods .............................................................................................................. 51
Data SRAM Configurations ........................................................................................................................ 52
Data and Tag SRAM Speed Requirements ................................................................................................. 52
DRAM Programmable Control ................................................................................................................... 53
DRAM Timing Mode - Read Cycle............................................................................................................ 53
DRAM Timing Mode - Write Cycle ........................................................................................................... 53
paR and MDfIDOE#.................................................................................................................................. 54
DRAM Row/Column MA to Address Bit Map .......................................................................................... 55
paR and AT Back-to-Back 110 Cycles ...................................................................................................... 57
VL Bus paR Signal Strapping.................................................................................................................... 59
;port B Register: Index 61h .......................................................................................................................... 63
DRAM Configuration Register 1: Index OOh.............................................................................................. 64
DRAM Control Register 1: Index Olh ........................................................................................................ 65
Cache Control Register 1: Index 02h .......................................................................................................... 65
Cache Control Register 2: Index 03h .......................................................................................................... 66
Shadow RAM Control Register 1: Index 04h ............................................................................................. 67
Shadow RAM Control Register 2: Index 05h ............................................................................................. 68
Shadow RAM Control Register 3: Index 06h ............................................................................................. 68
Python Chipset
DBS-Ol-CS002-1.0
Pageix

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