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PDF MMDF2P02E Data sheet ( Hoja de datos )
| Número de pieza | MMDF2P02E | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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MMDF2P02E
Power MOSFET
2 Amps, 25 Volts
P−Channel SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a low reverse recovery time. These devices
are designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc−dc
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives. The avalanche energy is
specified to eliminate the guesswork in designs where inductive loads
are switched and offer additional safety margin against unexpected
voltage transients.
Features
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• IDSS Specified at Elevated Temperatures
• Avalanche Energy Specified
• Mounting Information for SO−8 Package Provided
• This is a Pb−Free Device
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Drain Current − Continuous @ TA = 25°C
Drain Current − Continuous @ TA = 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
Total Power Dissipation @ TA = 25°C
(Note 2)
Derate above 25°C
VDSS
VGS
ID
ID
IDM
PD
25 Vdc
± 20 Vdc
2.5 Adc
1.7
13 Apk
2.0 W
16 mW/°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 10 Vdc, Peak
IL = 7.0 Apk, L = 10 mH, RG = 25 W)
Thermal Resistance, Junction−to−Ambient
(Note 2)
TJ, Tstg
EAS
RqJA
−55 to 150
245
62.5
°C
mJ
°C/W
Maximum Lead Temperature for Soldering
Purposes, 0.0625″ from case for 10 sec.
TL
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Negative sign for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with
one die operating, 10 sec. max.
http://onsemi.com
2 AMPERES, 25 VOLTS
RDS(on) = 250 mW
P−Channel
D
G
S
8
1
SO−8, Dual
CASE 751
STYLE 11
MARKING
DIAGRAM
8
F2PO2
AYWW G
G
1
F2P02 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Source−1
Gate−1
Source−2
Gate−2
18
27
36
45
Top View
Drain−1
Drain−1
Drain−2
Drain−2
ORDERING INFORMATION
Device
Package
Shipping†
MMDF2P02ER2G SO−8 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 9
1
Publication Order Number:
MMDF2P02E/D
1 page  
100
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25°C
MMDF2P02E
2
TJ = 25°C
VGS = 0 V
1.6
1.2
td(off)
tr
tf
td(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
0.8
0.4
0
0.6
0.8 1 1.2 1.4
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage
versus Current
1.6
di/dt = 300 A/ms
Standard Cell Density
trr
High Cell Density
trr
ta
tb
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RqJC).
This MOSFET can be safely used in switching circuits
with unclamped inductive loads. For reliable operation, the
stored energy from circuit inductance dissipated in the
transistor while in avalanche must be less than the rated limit
and must be adjusted for operating conditions differing from
those specified. Although industry practice is to rate in terms
of energy, avalanche energy capability is not a constant. The
energy rating decreases non−linearly with an increase of
peak current in avalanche and peak junction temperature.
Although many MOSFETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
http://onsemi.com
5
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