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PDF CD4006 Data sheet ( Hoja de datos )
| Número de pieza | CD4006 | |
| Descripción | CMOS 18-Stage Static Register | |
| Fabricantes | SYC | |
| Logotipo |  |
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CD4006
CMOS 18-Stage Static Register
Features
Pinout
• High-Voltage Type (20V Rating)
• Fully Static Operation
• Shifting Rates Up to 12MHz at 10V (typ)
• Permanent Register Storage with Clock Line High or
Low - No Information Recirculation Required
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
CD4006BM
TOP VIEW
D1 1
D1 + 4’ 2
CLOCK 3
D2 4
D3 5
D4 6
VSS 7
14 VDD
13 D1 + 4
12 D2 + 5
11 D2 + 4
10 D3 + 4
9 D4 + 5
8 D4 + 4
Functional Diagram
VDD
14
Applications
• Serial Shift Registers
• Frequency Division
• Time Delay Circuits
Description
CD4006BMS types are composed of 4 separate shift register
sections: two sections of four stages and two sections of five
stages with an output tap at the fourth stage. Each section has
an independent single-rail data path.
A common clock signal is used for all stages. Data are shifted
to the next stages on negative-going transitions of the clock.
Through appropriate connections of inputs and outputs, multi-
ple register sections of 4, 5, 8, and 9 stages or single register
sections of 10, 12, 13, 14, 16, 17 and 18 stages can be imple-
mented using one CD4006BMS package. Longer shift register
sections can be assembled by using more than one
CD4006BMS.
To facilitate cascading stages when clock rise and fall times are
slow, an optional output (D1 + 4’) that is delayed one-half clock-
cycle, is provided (see Truth Table for Output from Term. 2).
The CD4006BMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP H4Q
Frit Seal DIP
H6D
Ceramic Flatpack H4F
1
D1
4
STAGE
D2
CLOCK
D3
4
3
5
4
STAGE
4
STAGE
6
D4
4
STAGE
LATCH
1
STAGE
13
D1 + 4
2
D1 + 4’
12
D2 + 5
11
10 D2 + 4
D3 + 4
1
STAGE
9
D4 + 5
8
D4 + 4
7
VSS
www.sycelectronica.com.ar
1 page  
Specifications CD4006BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
OPEN
2, 8 - 13
GROUND
1, 3 - 7
VDD
14
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
Note 1
2, 8 - 13
7 1, 3 - 6, 14
Dynamic Burn-
In Note 1
2
7
14 8 - 13
3 1, 4 - 6
Irradiation
Note 2
2, 8 - 13
7 1, 3 - 6, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CD4006.PDF ] | |
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