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XC9500XL PDF даташит

Спецификация XC9500XL изготовлена ​​​​«Xilinx» и имеет функцию, называемую «High-Performance CPLD».

Детали детали

Номер произв XC9500XL
Описание High-Performance CPLD
Производители Xilinx
логотип Xilinx логотип 

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XC9500XL Даташит, Описание, Даташиты
k
0
R XC9500XL High-Performance CPLD
Family Data Sheet
DS054 (v2.5) May 22, 2009
0 0 Product Specification
Features
• Optimized for high-performance 3.3V systems
- 5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
- Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
- Pb-free available for all packages
- Lower power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Supports hot-plugging capability
- Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
• Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable
gates
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- 10,000 program/erase cycles endurance rating
- 20 year data retention
• Pin-compatible with 5V core XC9500 family in common
package footprints
Table 1: XC9500XL Device Family
XC9536XL
XC9572XL
XC95144XL
XC95288XL
Macrocells
Usable Gates
36 72 144 288
800
1,600
3,200
6,400
Registers
TPD (ns)
TSU (ns)
TCO (ns)
fSYSTEM (MHz)
36 72 144 288
5556
3.7 3.7 3.7 4.0
3.5 3.5 3.5 3.8
178 178 178 208
© 1998–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS054 (v2.5) May 22, 2009
Product Specification
www.xilinx.com
1









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XC9500XL Даташит, Описание, Даташиты
R XC9500XL High-Performance CPLD Family Data Sheet
Table 2: XC9500XL Packages and User I/O Pins (not including 4 dedicated JTAG pins)
Package(1)
XC9536XL
XC9572XL
XC95144XL
PC44
34 34
-
PCG44
34 34
VQ44
34 34
-
VQG44
34 34
CS48
36 38
-
CSG48
36 38
VQ64
36 52
-
VQG64
36 52
TQ100
- 72 81
TQG100
72 81
CS144
- - 117
CSG144
117
TQ144
- - 117
TQG144
117
PQ208
---
PQG208
BG256
---
BGG256
FG256
---
FGG256
CS280
---
CSG280
Notes:
1. The letter "G" as the third character indicates a Pb-free package.
XC95288XL
-
-
-
-
-
-
117
117
168
168
192
192
192
192
192
192
DS054 (v2.5) May 22, 2009
Product Specification
www.xilinx.com
2









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XC9500XL Даташит, Описание, Даташиты
R XC9500XL High-Performance CPLD Family Data Sheet
JTAG Port
3
JTAG
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
3
1
2 or 4
I/O
Blocks
In-System Programming Controller
54
18
54
18
54
18
54
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block N
Macrocells
1 to 18
DS054_01_042001
Figure 1: XC9500XL Architecture
Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
Family Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9500XL device supports in-system pro-
gramming (ISP) and the full IEEE Std 1149.1 (JTAG) bound-
ary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx® Virtex®,
Spartan®-XL and XC4000XL FPGA families, allowing sys-
tem designers to partition logic optimally between fast inter-
face circuitry and high-density general purpose logic. As
shown in Table 1, logic density of the XC9500XL devices
ranges from 800 to 6400 usable gates with 36 to 288 regis-
ters, respectively. Multiple package options and associated
I/O capacity are shown in Table 2. The XC9500XL family
members are fully pin-compatible, allowing easy design
migration across multiple density options in a given package
footprint.
The XC9500XL architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V
DS054 (v2.5) May 22, 2009
Product Specification
www.xilinx.com
3










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