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PDF HY57V161610D-I Data sheet ( Hoja de datos )
| Número de pieza | HY57V161610D-I | |
| Descripción | 2 Banks x 512K x 16 Bit Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
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HY57V161610D-I
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of
524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.0V to 3.6V power supplyNote1)
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms
• JEDEC standard 400mil 50pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM/LDQM
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
• Programmable CAS Latency ; 1, 2, 3 Clocks
• Internal two banks operation
ORDERING INFORMATION
Part No.
HY57V161610DTC-55I
HY57V161610DTC-6I
HY57V161610DTC-7I
HY57V161610DTC-10I
Clock Frequency
183MHz
166MHz
143MHz
100MHz
Organization
Interface
2Banks x 512Kbits x 16
LVTTL
Package
400mil
50pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 0.3/Mar. 02
1
1 page  
HY57V161610D-I
CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
CI1 2.5 4 pF
A0 ~ A10, BA
CI2 2.5 5 pF
CKE, CS, RAS, CAS, WE, UDQM, LDQM
Data input / output capacitance DQ0 ~ DQ15
CI/O
4
6.5 pF
OUTPUT LOAD CIRCUIT
Output
Vtt=1.4V
RT=250 Ω
30pF
Output
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA= - 40°C to 85°C)
Parameter
Power Supply Voltage
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
VDD
IL
IO
VOH
VOL
Min.
3.0
-1
-1
2.4
-
Max
3.6
1
1
-
0.4
Note :
1.VDD(min) is 3.15V when HY57V161610DTC-7I operates at CAS latency=2 and tCK2=8.9ns.
2.VIN = 0 to 3.6V, All other pins are not under test = 0V
3.DOUT is disabled, VOUT=0 to 3.6V
Unit
V
uA
uA
V
V
Note
1
2
3
IOH = -4mA
IOL =+4mA
Rev. 0.3/Mar. 02
5
5 Page 
PACKAGE INFORMATION
400mil 50pin Thin Small Outline Package (TC)
1Mx16 Synchronous DRAM
HY57V161610D-I
UNIT : mm(inch)
10.262(0.4040)
10.059(0.3960)
11.938(0.4700)
11.735(0.4620)
1.2(0.0472)
1.0(0.0394)
0.646 REF
0.8(0.0315 BSC)
21.057(0.8290)
20.879(0.8220)
0.45(0.0177)
0.30(0.0118)
0.150(0.0059)
0.050(0.0020)
GAGE PLANE
0~5deg
0.597(0.023 5)
0.406(0.0160)
0.210(0.0083)
0.120(0.0118)
Rev. 0.3/Mar. 02
11
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| PDF Descargar | [ Datasheet HY57V161610D-I.PDF ] | |
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