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PDF CHL8505 Data sheet ( Hoja de datos )
| Número de pieza | CHL8505 | |
| Descripción | High-Efficiency 5V MOSFET Gate Driver | |
| Fabricantes | International Rectifier | |
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High‐Efficiency 5V MOSFET Gate Driver CHL8505
FEATURES
Ideal for Server Memory applications using +5V
Fixed 5V Gate Drive
Large drivers designed to drive 3nF in < 15ns
with +5V drive
Low‐side driver – 2A source/4A sink
High‐side driver – 2A source/2A sink
Transitions times & Propagation delays < 15ns
Integrated bootstrap diode
Capable of high switching frequencies from 200kHz
up to greater than 1MHz
Compatible with IR’s patented Active Tri‐Level
(ATL) PWM for fastest response to transient
overshoot
Non‐overlap and under voltage protection
Thermally enhanced 10‐pin DFN package
Lead free RoHS compliant package
Low Quiescent power to optimize efficiency
APPLICATIONS
Multiphase synchronous buck converter for Server
CPUs and DDR Memory VR solutions
High efficiency and compact VRM
Optimized for Sleep state S3 systems using +5VSB
Notebook Computer and Graphics VR solutions
DESCRIPTION
The CHL8505 MOSFET is a high‐efficiency gate driver which
can switch both high‐side and low‐side N‐channel external
MOSFETs in a synchronous buck converter. It is intended
for use with IR Digital PWM controllers to provide a total
voltage regulator (VR) solution for today’s advanced
computing applications.
The CHL8505 driver is capable of rapidly switching large
MOSFETs with low Rdson and large input capacitance used
in high‐efficiency designs. It is uniquely designed to
operate from a 5V source such as a system 5V or 5V
standby voltages in sleep states.
The CHL8505 has a unique circuit which improves drive
strength to the external MOSFETs even with just 5V
supplied at the VDRV pin. This insures faster switching
comparable to drivers designed for +12V drive operation.
The integrated boot diode reduces external component
count. The CHL8505 also features an adaptive non‐overlap
control for shoot‐through protection.
The CHL8505 is configured to drive both the high and low‐
side switches from the patented IR fast Active Tri‐Level
(ATL) PWM signal, which will optimize the turn off time of
individual phases, optimizing transient performance.
BASIC APPLICATION
Figure 1: CHL8505 Basic Application Circuit
PIN DIAGRAM
PWM 1
VCC 2
VDRV 3
NC 4
BOOT 5
Top View
GND
Pin 11
3x3 DFN
10 NC
9 NC
8 LO_GATE
7 SWITCH
6 HI_GATE
Figure 2: CHL8505 Package Top View
1 December 6, 2011 | FINAL | V1.05
1 page  
PIN DESCRIPTIONS
High‐Efficiency 5V MOSFET Gate Driver CHL8505
PIN#
1
2
3
4
5
6
7
8
9
10
PAD (11)
PIN NAME
PIN DESCRIPTION
PWM
VCC
VDRV
NC
BOOT
HI_GATE
SWITCH
LO_GATE
NC
NC
GND
The PWM signal is the control input for the driver from a 1.8V IR ATL‐based PWM signal. Connect this pin
to the PWM output of the controller.
Connect this pin to a +5V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to a separate supply voltage between 4.0V and 13.2V to vary the drive voltage on the
low‐side MOSFETs. Place a high quality low ESR ceramic capacitor from this pin to GND.
Leave this pin floating.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and
the SWITCH pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal
Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
Upper gate drive output. Connect to gate of high‐side power N‐Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET.
This pin provides a return path for the upper gate drive
Lower gate drive output. Connect to gate of the low‐side power N‐Channel MOSFET.
Leave this pin floating.
Leave this pin floating.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return
of the driver.
5 December 6, 2011 | FINAL | V1.05
5 Page 
High‐Efficiency 5V MOSFET Gate Driver CHL8505
THEORY OF OPERATION
POWER‐ON RESET (POR)
The CHL8505 incorporates a power‐on reset feature.
This ensures that both the high‐ and low‐side output
drivers are made active only after the device supply
voltage has exceeded a certain minimum operating
threshold. The Vcc and Vdrv supply is monitored and both
the drivers are set to the low state, holding both external
MOSFETs off. Once Vcc and Vdrv crosses the rising POR
threshold, the CHL8505 is reset and the outputs are held in
the low state until a transition from tri‐state to active
operation is detected at the PWM input. During normal
operation the drivers continue to remain active until the
Vcc and Vdrv falls below the falling POR threshold.
INTEGRATED BOOTSTRAP DIODE
The CHL8505 features an integrated bootstrap diode to
reduce external component count. This enables the
CHL8505 to be used effectively in cost and space sensitive
designs.
The bootstrap circuit is used to establish the gate voltage
for the high‐side driver. It consists of a diode and capacitor
connected between the SWITCH and BOOT pins of the
device. Integrating the diode within the CHL8505,
results in the need for an external boot capacitor only.
The bootstrap capacitor is charged through the diode
and injects this charge into the high‐side MOSFET input
capacitance when PWM signal goes high.
IR ACTIVE TRI‐LEVEL (ATL) PWM INPUT SIGNAL
The CHL8505 gate drivers are driven by a patented tri‐level
PWM control signal provided by the IR digital PWM
controllers. During normal operation, the rising and falling
edges of the PWM signal transitions between 0V and 1.8V
to switch the LO_GATE and HI_GATE. To force both driver
outputs low simultaneously, the PWM signal crosses a
tri‐state voltage level higher than the tri‐state HI_GATE
threshold. This threshold based tri‐state results in a very
fast disable for both the drivers, with only a small tri‐state
propagation delay. MOSFET switching resumes when the
PWM signal falls below the tri‐state threshold into the
normal operating voltage range.
This fast tri‐state operation eliminates the need for any
tri‐state hold‐off time of the PWM signal to dwell in the
shutdown window. Dedicated disable or enable pins are
not required which simplifies the routing and layout in
11 December 6, 2011 | FINAL | V1.05
applications with a limited number of board layers. It also
provides switching free of shoot through for slow PWM
transition times of up to 20ns. The CHL8505 is therefore
tolerant of stray capacitance on the PWM signal lines.
The CHL8505 provides a 1.0mA typical pull‐up current to
drive the PWM input to the tri‐state condition of 3.3V
when the PWM controller output is in its high impedance
state. The 1.0mA typical current is designed for driving
worst case stray capacitances and transition the CHL8505
into the tri‐state condition rapidly to avoid a prolonged
period of conduction of the high‐ or low‐side MOSFETs
during faults. Immediately after the driver is driven into
the tri‐state mode, the 1mA current is disables such that
power is conserved.
DIODE EMULATION DURING LOAD RELEASE
One advantage of this fast tri‐state scheme is the ability
to quickly turn‐off all low‐side MOSFETs during a load
release event. This is known as diode emulation since all
the load current is forced to flow momentarily through
the body diodes of the MOSFETs. This results in a much
lower overshoot on the output voltage as can be seen in
Figure 7 below.
I_out 105A to 10A
V_out without diode emulation
Overshoots ~25mV over 0A level
V_out with Diode Emulation
Overshoot within 0A level
Results in reduction of 30mV
overshoot
Figure 7: Output Voltage Overshoot Reduction
with Diode Emulation
START UP
During initial startup, the CHL8505 holds both high‐ and
low‐side drivers low even after POR threshold is reached.
This mode is maintained while the PWM signal is pulled to
the tri‐state threshold level greater than the tri‐state
HI_GATE threshold and until it transitions out of tri‐state.
It is this initial transition out of the tri‐state which enables
both drivers to switch based on the normal PWM voltage
levels.
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CHL8505.PDF ] | |
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