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Спецификация 555 изготовлена ​​​​«ETC» и имеет функцию, называемую «Timer IC».

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Номер произв 555
Описание Timer IC
Производители ETC
логотип ETC логотип 

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555 Даташит, Описание, Даташиты
The 555 Timer IC
(Adapted from http://www.electronics.dit.ie/staff/mtully/555%20folder/555%20timer.htm)
The 555 timer IC was first introduced around 1971 by the Signetics Corporation as the SE555/NE555 and was
called "The IC Time Machine" and was also the very first and only commercial timer IC available. It provided circuit
designers with a relatively cheap, stable, and user-friendly integrated circuit for both monostable and astable
applications. Since this device was first made commercially available, a myriad of novel and unique circuits have
been developed and presented in several trade, professional, and hobby publications. The past ten years some
manufacturers stopped making these timers because of competition or other reasons. Yet other companies, like
NTE (a subdivision of Philips) picked up where some left off.
Although these days the CMOS version of this IC, like the Motorola MC1455, is mostly used, the regular type is
still available, however there have been many improvements and variations in the circuitry. But all types are pin-for-
pin plug compatible.
In this tutorial the 555 timer is examined in detail along with its uses, either by itself or in combination with other
solid state devices. This timer uses a maze of transistors, diodes and resistors and for this complex reason a more
simplified (but accurate) block diagram is used to
explain the internal organizations of the 555.
The 555, in fig. 1 and fig. 2 above, comes in
two packages, either the round metal-can called
the 'T' package or the more familiar 8-pin DIP 'V'
package. About 20-years ago the metal-can type
was pretty much the standard (SE/NE types). The
556 timer is a dual 555 version and comes in a
14-pin DIP package, the 558 is a quad version
with four 555's also in a 14 pin DIP case.
Inside the 555 timer, at fig. 3, are the
equivalent of over 20 transistors, 15 resistors, and
2 diodes, depending of the manufacturer. The
equivalent circuit, in block diagram, providing the
functions of control, triggering, level sensing or
comparison, discharge, and power output. Some
of the more attractive features of the 555 timer
are: Supply voltage between 4.5 and 18 volt,
supply current 3 to 6 mA, and a Rise/Fall time of
100 nSec. It can also withstand quite a bit of
abuse. The Threshold current determine the
maximum value of Ra + Rb. For 15 volt operation
the maximum total resistance for R (Ra +Rb) is 20
MΩ.
The supply current, when the output is 'high', is typically 1 milli-amp (mA) or less. The initial monostable timing
accuracy is typically within 1% of its calculated value, and exhibits negligible (0.1%/V) drift with supply voltage.
Thus long-term supply variations can be ignored, and the temperature variation is only 50ppm/°C (0.005%/°C).
All IC timers rely upon an external capacitor to determine the off-on time intervals of the output pulses. It takes
a finite period of time for a capacitor (C) to charge or discharge through a resistor (R). Those times are clearly
defined and can be calculated given the values of resistance and capacitance.









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555 Даташит, Описание, Даташиты
The basic RC charging circuit is shown in fig. 4. Assume that the capacitor is initially discharged. When the
switch is closed, the capacitor begins to charge through the
resistor. The voltage across the capacitor rises from zero up to the
value of the applied DC voltage. The charge curve for the circuit is
shown in fig. 6. The time that it takes for the capacitor to charge to
63.7% of the applied voltage is known as the time constant (t). That
time can be calculated with the simple expression:
t=RXC
Assume a resistor value of 1 MΩ and a capacitor value of 1uF.
The time constant in that case is:
t = 1,000,000 X 0.000001 = 1 second
Assume further that the applied voltage is 6 volts. That means
that it will take one time constant for the voltage across the
capacitor to reach 63.2% of the applied voltage. Therefore, the
capacitor charges to approximately 3.8 volts in one second.
Fig. 4-1, Change in the input pulse frequency allows completion of
the timing cycle. As a
general rule, the
monostable 'ON'
time is set approximately 1/3 longer than the expected time between
triggering pulses. Such a circuit is also known as a 'Missing Pulse
Detector'.
Looking at the curve in fig. 6. you can see that it takes
approximately 5 complete time constants for the capacitor to charge
to almost the applied voltage. It would take about 5 seconds for the
voltage on the capacitor to rise to approximately the full 6-volts.
Definition of Pin Functions:
Refer to the internal 555 schematic of Fig. 4-2
Pin 1 (Ground): The ground (or common) pin is the most-negative supply potential of the device, which is normally
connected to circuit common (ground) when operated from positive supply voltages.
Pin 2 (Trigger): This pin is the input to the lower comparator and is used to set the latch, which in turn causes the
output to go high. This is the beginning of the timing sequence in monostable operation. Triggering is accomplished
by taking the pin from above to below a voltage level of 1/3 V+ (or, in general, one-half the voltage appearing at pin
5). The action of the trigger input is level-sensitive, allowing slow rate-of-change waveforms, as well as pulses, to
be used as trigger sources. The trigger pulse must be of shorter duration than the time interval determined by the









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555 Даташит, Описание, Даташиты
external R and C. If this pin is held low longer than that, the output will remain high until the trigger input is driven
high again.
One precaution that should be observed with the trigger input signal is that it must not remain lower than 1/3 V+ for
a period of time longer than the timing cycle. If this is allowed to happen, the timer will retrigger itself upon
termination of the first output pulse. Thus, when the timer is driven in the monostable mode with input pulses longer
than the desired output pulse width, the input trigger should effectively be shortened by differentiation.
The minimum-allowable pulse width for triggering is somewhat dependent upon pulse level, but in general if it is
greater than the 1uS (micro-Second), triggering will be reliable.
A second precaution with respect to the trigger input concerns storage time in the lower comparator. This portion of
the circuit can exhibit normal turn-off delays of several microseconds after triggering; that is, the latch can still have
a trigger input for this period of time after the trigger pulse. In practice, this means the minimum monostable output
pulse width should be in the order of 10uS to prevent possible double triggering due to this effect.
The voltage range that can safely be applied to the trigger pin is between V+ and ground. A dc current, termed the
trigger current, must also flow from this terminal into the external circuit. This current is typically 500nA (nano-amp)
and will define the upper limit of resistance allowable from pin 2 to ground. For an astable configuration operating at
V+ = 5 volts, this resistance is 3 Mega-ohm; it can be greater for higher V+ levels.
Pin 3 (Output): The output of the 555 comes from a high-current totem-pole stage made up of transistors Q20 -
Q24. Transistors Q21 and Q22 provide drive for source-type loads, and their Darlington connection provides a high-
state output voltage about 1.7 volts less than the V+ supply level used. Transistor Q24 provides current-sinking
capability for low-state loads referred to V+ (such as typical TTL inputs). Transistor Q24 has a low saturation
voltage, which allows it to interface directly, with good noise margin, when driving current-sinking logic. Exact
output saturation levels vary markedly with supply voltage, however, for both high and low states. At a V+ of 5 volts,
for instance, the low state Vce(sat) is typically 0.25 volts at 5 mA. Operating at 15 volts, however, it can sink 200mA
if an output-low voltage level of 2 volts is allowable (power dissipation should be considered in such a case, of
course). High-state level is typically 3.3 volts at V+ = 5 volts; 13.3 volts at V+ = 15 volts. Both the rise and fall times
of the output waveform are quite fast, typical switching times being 100nS.
The state of the output pin will always reflect the inverse of the logic state of the latch, and this fact may be seen by
examining Fig. 3. Since the latch itself is not directly accessible, this relationship may be best explained in terms of
latch-input trigger conditions. To trigger the output to a high condition, the trigger input is momentarily taken from a
higher to a lower level. [see "Pin 2 - Trigger"]. This causes the latch to be set and the output to go high. Actuation of
the lower comparator is the only manner in which the output can be placed in the high state. The output can be
returned to a low state by causing the threshold to go from a lower to a higher level [see "Pin 6 - Threshold"], which
resets the latch. The output can also be made to go low by taking the reset to a low state near ground [see "Pin 4 -
Reset"].
The output voltage available at this pin is approximately equal to the Vcc applied to pin 8 minus 1.7V.
Pin 4 (Reset): This pin is also used to reset the latch and return the output to a low state. The reset voltage
threshold level is 0.7 volt, and a sink current of 0.1mA from this pin is required to reset the device. These levels are
relatively independent of operating V+ level; thus the reset input is TTL compatible for any supply voltage.
The reset input is an overriding function; that is, it will force the output to a low state regardless of the state of either
of the other inputs. It may thus be used to terminate an output pulse prematurely, to gate oscillations from "on" to
"off", etc. Delay time from reset to output is typically on the order of 0.5 µS, and the minimum reset pulse width is
0.5 µS. Neither of these figures is guaranteed, however, and may vary from one manufacturer to another. In short,
the reset pin is used to reset the flip-flop that controls the state of output pin 3. The pin is activated when a voltage
level anywhere between 0 and 0.4 volt is applied to the pin. The reset pin will force the output to go low no matter
what state the other inputs to the flip-flop are in. When not used, it is recommended that the reset input be tied to
V+ to avoid any possibility of false resetting.
Pin 5 (Control Voltage): This pin allows direct access to the 2/3 V+ voltage-divider point, the reference level for
the upper comparator. It also allows indirect access to the lower comparator, as there is a 2:1 divider (R8 - R9) from
this point to the lower-comparator reference input, Q13. Use of this terminal is the option of the user, but it does
allow extreme flexibility by permitting modification of the timing period, resetting of the comparator, etc.
When the 555 timer is used in a voltage-controlled mode, its voltage-controlled operation ranges from about 1 volt
less than V+ down to within 2 volts of ground (although this is not guaranteed). Voltages can be safely applied
outside these limits, but they should be confined within the limits of V+ and ground for reliability.
By applying a voltage to this pin, it is possible to vary the timing of the device independently of the RC network. The
control voltage may be varied from 45 to 90% of the Vcc in the monostable mode, making it possible to control the
width of the output pulse independently of RC. When it is used in the astable mode, the control voltage can be
varied from 1.7V to the full Vcc. Varying the voltage in the astable mode will produce a frequency modulated (FM)
output.










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