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A3V56S30GTP PDF даташит

Спецификация A3V56S30GTP изготовлена ​​​​«Zentel» и имеет функцию, называемую «256M Single Data Rate Synchronous DRAM».

Детали детали

Номер произв A3V56S30GTP
Описание 256M Single Data Rate Synchronous DRAM
Производители Zentel
логотип Zentel логотип 

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A3V56S30GTP Даташит, Описание, Даташиты
A3V56S30GTP
A3V56S40GTP
256M Single Data Rate Synchronous DRAM
256Mb Synchronous DRAM Specification
A3V56S30GTP
A3V56S40GTP
Industrial Version
Zentel Electronics Corp.
I Revision 1.0
Jun., 2013









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A3V56S30GTP Даташит, Описание, Даташиты
A3V56S30GTP
A3V56S40GTP
256M Single Data Rate Synchronous DRAM
General Description
A3V56S30GTP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and
A3V56S40GTP is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of
CLK. A3V56S30GTP and A3V56S40GTP achieve very high speed data rates up to 166MHz, and are suitable for main
memories or graphic memories in computer systems.
Features
- Single 3.3V ±0.3V power supply
- Maximum clock frequency:
-60:166MHz<3-3-3>/-70:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0, BA1 (Bank Address)
- CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQM (A3V56S30GTP), LDQM and UDQM (A3V56S40GTP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Support concurrent auto-precharge
- Auto and self refresh
- 8192 refresh cycles /64ms
- Temperature range: -40to +85
- AEC-Q100 Grade3 compliant
- LVTTL Interface
- Package:
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Pb-free package is available
Ordering Information
Part
Number
A3V56S30GTP-60I
A3V56S30GTP-70I
A3V56S30GTP-75I
A3V56S40GTP-60I
A3V56S40GTP-70I
A3V56S40GTP-75I
Organization
(words x bits)
32M x 8
16M x 16
Max.
Frequency
166MHz
143MHz
133MHz
166MHz
143MHz
133MHz
CAS
Latency
3
Supply
Voltage
3.3V
Zentel Electronics reserves the right to change products or specification without notice.
I Revision 1.0
Page 1 / 39
Jun., 2013









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A3V56S30GTP Даташит, Описание, Даташиты
A3V56S30GTP
A3V56S40GTP
256M Single Data Rate Synchronous DRAM
Pin Configuration (Top View)
x8
x16
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
PIN CONFIGURATION
(TOP VIEW)
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-7
DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O (A3V56S30GTP)
: Data I/O (A3V56S40GTP)
DQM : Output Disable / Write Mask (A3V56S30GTP)
U,L DQM : Output Disable / Write Mask (A3V56S40GTP)
A0-12 : Address Input
BA0,1 : Bank Address
VDD : Power Supply
VDDQ : Power Supply for Output
VSS : Ground
VSSQ
: Ground for Output
I Revision 1.0
Page 2 / 39
Jun., 2013










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Номер в каталогеОписаниеПроизводители
A3V56S30GTP256M Single Data Rate Synchronous DRAMZentel
Zentel

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