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PDF NB7VQ572M Data sheet ( Hoja de datos )
| Número de pieza | NB7VQ572M | |
| Descripción | 1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator | |
| Fabricantes | ON Semiconductor | |
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NB7VQ572M
1.8V / 2.5V /3.3V Differential
4:1 Mux w/Input Equalizer
to 1:2 CML Clock/Data
Fanout / Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB7VQ572M is a high performance differential 4:1 Clock /
Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 7 GHz / 10 Gbps respectively with a 1.8 V, 2.5 V, or
3.3 V power supply.
Each INx / INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB7V572M, which is pin−compatible to the
NB7VQ572M.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB7VQ572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
As such, the NB7VQ572M is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The two differential CML outputs will swing 400 mV when externally
loaded and terminated with a 50 W resistor to VCC and are optimized
for low skew and minimal jitter.
The NB7VQ572M is offered in a low profile 5x5 mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com. The NB7VQ572M
is a member of the GigaComm™ family of high performance clock
products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7V
Q572M
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
Features
• Input Data Rate > 10 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:2 CML Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML,
LVDS
• 175 ps Typical Propagation Delay
• 45 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak,
Typical
• Operating Range: VCC = 1.71 V to 3.6 V with GND =
0V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN−32 Package, 5mm x 5mm, Pb−Free
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
October, 2010 − Rev. P0
1
Publication Order Number:
NB7VQ572M/D
1 page  
NB7VQ572M
Table 5. DC CHARACTERISTICS CML OUTPUT VCC = 1.71 V to 3.6 V , GND = 0 V, TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min Typ Max
POWER SUPPLY
VCC Power Supply Voltage
VVCCCC
=
=
3.3
2.5
V
V
3.0
2.375
3.3
2.5
3.6
2.625
VCC = 1.8 V
1.71
1.8
1.89
ICC Power Supply Current for VCC (Inputs and Outputs Open)
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
130 160
120 145
100 120
CML OUTPUTS (Note 6)
VOH Output HIGH Voltage
VOL Output LOW Voltage
VOL Output LOW Voltage
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 3.3 V
VCC = 2.5 V
VCC =1.8 V
VCC = 3.3 V
VC3C27−030
2470
1770
VCC − 550
2675
1875
VCC − 625
2675
V3C2C9−5 5
2495
1795
VCC − 450
2825
2025
1325
VCC − 475
2825
3V3C0C0
2500
1800
VCC − 350
2975
2175
1475
VCC − 325
2975
Unit
V
mA
mV
mV
mV
VCC = 2.5 V VCC − 600
1900
VCC – 475
2025
VCC − 350
2150
VCC =1.8 V VCC − 550
1250
VCC – 450
1350
VCC − 350
1450
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 7 and 8) (Note 7)
VIH
VIL
Vth
VISE
VREFAC
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage (VIH − VIL)
Vth + 100
GND
1100
200
VREFAC Output Reference Voltage (100 mA Load)
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC − 800
VCC − 750
1050
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 and 10) (Note 9)
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN, IN)
Differential Input Voltage (IN, IN) (VIHD − VILD)
Input Common Mode Range (Differential Configuration,
Note 10) (Figure 11)
1200
0
100
1150
VCC − 625
VCC − 575
VCC − 525
VCC
Vth − 100
VCC − 100
1200
VCC − 500
VCC − 450
VCC − 400
VCC
VIHD − 100
1200
VCC − 50
mV
mV
mV
mV
mV
mV
mV
mV
mV
IIH Input HIGH Current IN / IN (VTIN/VTIN Open)
IIL Input LOW Current IN / IN (VTIN/VTIN Open)
CONTROL INPUT (SELx Pin)
−150
−150
150 mA
150 mA
VIH Input HIGH Voltage for Control Pin
VIL Input LOW Voltage for Control Pin
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
VCC x 0.65
GND
−150
−150
VCC
VCC x 0.35
150
150
V
V
mA
mA
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55 W
RTOUT
Internal Output Termination Resistor
45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with VCC.
6. CML outputs loaded with 50 W to VCC for proper operation.
7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
5
5 Page 
NB7VQ572M
PACKAGE DIMENSIONS
ÉÉÉÉPIN ONE
LOCATION
D
QFN32 5*5*1 0.5 P
CASE 488AM−01
A ISSUE O
B
E
2 X 0.15 C
TOP VIEW
2 X 0.15 C
0.10 C
32 X 0.08 C
(A3)
SIDE VIEW A1
A
SEATING
PLANE
C
L
32 X
EXPOSED PAD
9
D2
16 17
K
32 X
8
E2
1
32
32 X b
0.10 C A B
0.05 C
24
25
e
32 X
0.63
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN NOM MAX
A 0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b 0.180 0.250 0.300
D 5.00 BSC
D2 2.950 3.100 3.250
E 5.00 BSC
E2 2.950 3.100 3.250
e 0.500 BSC
K 0.200 −−− −−−
L 0.300 0.400 0.500
SOLDERING FOOTPRINT*
5.30
3.20
3.20 5.30
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB7VQ572M/D
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet NB7VQ572M.PDF ] | |
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