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PDF NB7L1008 Data sheet ( Hoja de datos )
| Número de pieza | NB7L1008 | |
| Descripción | 2.5V / 3.3V 1:8 LVPECL Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB7L1008
2.5V / 3.3V 1:8 LVPECL
Fanout Buffer
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L1008 is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008 produces eight identical output copies
of Clock or Data operating up to 7 GHz or 12 Gb/s, respectively. As
such, the NB7L1008 is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pin. This feature allows the NB7L1008 to
accept various logic standards, such as LVPECL, CML, LVDS logic
levels. The VREFAC reference output can be used to rebias
capacitor−coupled differential or single−ended input signals. The 1:8
fanout design was optimized for low output skew applications. The
NB7L1008 is a member of the GigaComm™ family of high
performance clock products.
Features
• Typical Maximum Input Data Rate > 12 Gb/s Typical
• Data Dependent Jitter < 15 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:8 LVPECL Outputs, < 20 ps max
• Multi−Level Inputs, accepts LVPECL, CML, LVDS
• 160 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
• Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V
• Internal Input Termination Resistors, 50 W
• VREFAC Reference Output
• QFN−32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free and Halide−Free Devices
http://onsemi.com
MARKING
32 DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
1008
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
SIMPLIFIED LOGIC DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
IN
50W
VT
50W
IN
VREFAC
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
1 Publication Order Number:
NB7L1008/D
1 page  
NB7L1008
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0V TA = −40°C to 85°C (Note 10)
Symbol
Characteristic
Min Typ
Max Unit
fDATA
fINCLK
VOUTPP
VCMR
Maximum Operating Input Data Rate (Note 17)
Maximum Input Clock Frequency, VOUTPP w 400 mV (Note 17)
Output Voltage Amplitude
(see Figures 2 and 6, Notes 11, 17)
fin v 5 GHz
Input Common Mode Range (Differential Configuration,
Note 12, Figure 10)
10
5
400
600
12 Gb/s
7 GHz
mV
VCC − 50
mV
tPLH, tPHL Propagation Delay to Output Differential, IN/IN to Qn/Qn
100 160 220 ps
tPLH TC Propagation Delay Temperature Coefficient −40°C to +85°C
25 fs/°C
tDC Output Clock Duty Cycle fin v 5 GHz
45 49/51 55 %
tSKEW
Within Device Skew (Note 13)
Device to Device Skew (Note 14)
20 ps
100
Tjitter
Clock Jitter RMS, 1000 Cycles (Note 17) fin ≤ 6 GHz
Data Dependent Jitter (DDJ) (Note 17) ≤ 10 Gb/s
0.2 0.8 ps
3 15
Tjitter
(additive)
VINPP
622 MHz @ Integration Range of 12 kHz to 20 MHz
Input Voltage Swing (Differential Configuration) (Note 16)
(Figure 6)
0.025
ps
100
1200
mV
tr, tf Output Rise/Fall Times (20% − 80%) Qn, Qn
20 50 80 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. All outputs must be loaded with external 50 W to VCC − 2 V.
11. Output voltage swing is a single−ended measurement operating in differential mode.
12. VIHDMIN ≥ 1100 mV.
13. Within device skew compares coincident edges.
14. Device to device skew is measured between outputs under identical transition
15. Additive CLOCK jitter with 50% duty cycle clock signal input.
16. Input voltage swing is a single−ended measurement operating in differential mode.
17. VCC of 2.5−3.3, input = 800 mvp−p
.
1.0
VCC
0.9
0.8
0.7 IN
50 W
0.6
VT
0.5 50 W
Vout p−p
IN
0.4
0.3
2
3
45 67
8 9 10
FREQUENCY (GHz)
Figure 2. Typical VOUT P−P vs. Frequency at 255C
Figure 3. Input Structure
http://onsemi.com
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| PDF Descargar | [ Datasheet NB7L1008.PDF ] | |
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