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NB3N2302 PDF даташит

Спецификация NB3N2302 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «3.3V / 5V 5MHz to 133MHz Frequency Multiplier and Zero Delay Buffer».

Детали детали

Номер произв NB3N2302
Описание 3.3V / 5V 5MHz to 133MHz Frequency Multiplier and Zero Delay Buffer
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NB3N2302 Даташит, Описание, Даташиты
NB3N2302
3.3V / 5V 5MHz to 133MHz
Frequency Multiplier and
Zero Delay Buffer
Description
The NB3N2302 is a versatile Zero Delay Buffer that operates from
5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a
reference input and drives a B1 and a B2 clock output. The
NB3N2302 has an onchip PLL which locks to the input reference
clock presented on the REF_IN pin. The PLL feedback is required to
be driven to the FBIN pin and can be obtained by connecting either the
OUT1 or OUT2 pin to the FBIN pin.
The Function Select inputs control the various multiplier output
frequency combinations as shown in Table 1.
Features
Output Frequency Range: 5 MHz to 133 MHz
Two LVTTL/LVCMOS Outputs
65 ps Typical Jitter OUT2
115 ps Typical Jitter OUT1
25 ps Typical OutputtoOutput Skew
Operating Voltage Range: VDD = 3.3 V $5% or 5 V $10%
Clock Multiplication of the Reference Input Frequency, See Table 1
for Options
Packaged in 8Pin SOIC
40°C to +85°C Ambient Operating Temperature Range
Ideal for PCIX and Networking Clocks
These are PbFree Devices
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
2302
A
L
Y
W
G
MARKING DIAGRAM
8
3N2302
ALYWG
G
1
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
External feedback connection
to OUT1 or OUT2, not both
FS0
FS1
REF_IN
FBIN
Select Input
Decoding
PLL
÷2
OUT1
OUT2
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2011
October, 2011 Rev. 1
1
Publication Order Number:
NB3N2302/D









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NB3N2302 Даташит, Описание, Даташиты
NB3N2302
FBIN 1
REF_IN 2
GND 3
FS0 4
8 OUT2
7 VDD
6 OUT1
5 FS1
Figure 2. NB3N2302 Package Pinout (Top View) 8pin SOIC (150 mil)
Table 1. CLOCK MULTIPLIER SELECT TABLE
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
OUT1
2 x REF
4 x REF
REF
8 x REF
4 x REF
8 x REF
2 x REF
16 x REF
OUT2
REF
2 x REF
REF / 2
4 x REF
2 x REF
4 x REF
REF
8 x REF
REF_IN Min
(MHz)
5
5
10
5
5
5
5
5
REF_IN Max
(MHz)
66.5
33.25
133
16.625
33.25
16.625
66.5
8.3125
Table 2. PIN DESCRIPTION
Pin #
Pin
Name
Type
1
FBIN
LVCMOS/LVTTL
Input
2 REF_IN LVCMOS/LVTTL
Input
3 GND
Power
4 FS0 LVCMOS/LVTTL
Input
5 FS1 LVCMOS/LVTTL
Input
6
OUT1
LVCMOS/LVTTL
Output
7 VDD
Power
8
OUT2
LVCMOS/LVTTL
Output
Description
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations are synchronized to the REF signal input (REF_IN).
Reference Input: The output signals are synchronized to this signal.
Negative supply voltage; Connect to ground, 0 V
Function Select Input: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Function Select Input: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Positive supply voltage This pin should be bypassed with a 0.1 mF decoupling capacitor.
Use ferrite beads to help reduce noise for optimal jitter performance.
Output 2: The frequency of the signal provided by this pin is onehalf of the frequency of
OUT1. See Table 1.
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NB3N2302 Даташит, Описание, Даташиты
NB3N2302
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
> 2 kV
> 200 V
Level 1
UL 94 VO @ 0.125 in
6910 Devices
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1 Condition 2
Rating
Unit
VDD, VIN
TA
Voltage on any pin
Operating Temperature Range,
Commercial
Industrial
GND = 0 V
–0.5 to +7.0
0 to +70
40 to +85
V
°C
Tstg Storage Temperature Range
TB Ambient Temperature under Bias
qJA Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
SOIC8
SOIC8
65 to +150
–55 to +125
190
130
°C
°C
°C/W
PD Power Dissipation
0.5 W
qJC Thermal Resistance (JunctiontoCase)
(Note 2)
SOIC8
42 °C/W
TSOL Wave Solder PbFree
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board 2S2P (2 signal, 2 power
http://onsemi.com
3










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