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PDF CAV93C66 Data sheet ( Hoja de datos )
| Número de pieza | CAV93C66 | |
| Descripción | EEPROM | |
| Fabricantes | ON Semiconductor | |
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CAV93C66
4 Kb Microwire Serial CMOS
EEPROM
Description
The CAV93C66 is a 4 Kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at VCC) or 512
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The device features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• High Speed Operation: 2 MHz
• 2.5 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Sequential Read
• Software Write Protection
• Power−up Inadvertent Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• 8−lead SOIC and TSSOP Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
ORG
CS
SK
DI
CAV93C66
DO
GND
Figure 1. Functional Symbol
Note: When the ORG pin is connected to VCC, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
CS 1
SK
DI
DO
VCC
NC
ORG
GND
SOIC (V), TSSOP (Y)
(Top View)
Pin Name
CS
SK
DI
DO
VCC
GND
ORG
NC
PIN FUNCTION
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
December, 2013 − Rev. P0
1
Publication Order Number:
CAV93C66/D
1 page  
CAV93C66
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAV93C66 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAV93C66 after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAV93C66 write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status. The
EWEN and EWDS instructions timing is shown in Figure 4.
SK
CS
AN AN−1
DI
11
0
A0
tPD0
DO HIGH−Z
Don’t Care
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Figure 3. READ Instruction Timing
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
http://onsemi.com
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