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FUSB1501 PDF даташит

Спецификация FUSB1501 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «USB2.0 Full-Speed / Low-Speed Transceiver».

Детали детали

Номер произв FUSB1501
Описание USB2.0 Full-Speed / Low-Speed Transceiver
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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FUSB1501 Даташит, Описание, Даташиты
April 2011
FUSB1500 — USB2.0 Full-Speed /
Low-Speed Transceiver with Charger Detection
Features
Complies with USB2.0 Specification
Supports 12Mbps and 1.5Mbps USB2.0 Speeds
- Single Ended (SE) Mode Signaling
- Slew-Rate Controlled Differential Data Driver
- Differential Input Receiver with Wide Common-
Mode Range and High Input Sensitivity
- Stable RCV Output during SE0 Condition
- Two Single-Ended Receivers with Hysteresis
Supports I/O Voltage: 1.65V to 3.6V
Applications
Dual-Camera Applications for Cell Phones
Dual-LCD Applications for Cell Phones, Digital
Camera Displays, and Viewfinders
Description
The FUSB1500 is a USB2.0 FS/LS transceiver with
resistive charger detection. It is compliant with the
Universal Serial Bus Specification, Rev. 2.0 (USB2.0).
Ideal for portable electronic devices; such as mobile
phones, digital still cameras, and personal digital
assistants; it allows USB Application Specific ICs
(ASICs) and Programmable Logic Devices (PLDs) with
power supply voltages from 1.65V to 3.6V to interface
with the physical layer of the Universal Serial Bus.
The FUSB1500 can be used as a USB device
transceiver or a USB host transceiver. It can transmit
and receive serial data at both full-speed (12Mbps) and
low-speed (1.5Mbps) data rates.
The FUSB1500 supports the SE Mode controller
interface.
IMPORTANT NOTE:
For additional performance information, please contact
Ordering Information
Part Number
FUSB1500MHX
Operating
Temperature
Range
-40 to +85°C
Top
Mark
FUSB
1500
Package
16-Pin, Molded Leadless Package (MLP),
JEDEC MO217 Equivalent, 3mm Square
Packing
Method
Tape and Reel
© 2008 Fairchild Semiconductor Corporation
FUSB1500 • Rev. 1.0.1
www.fairchildsemi.com









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FUSB1501 Даташит, Описание, Даташиты
Block Diagram
INT_N
SUSPEND
SPEED_N
CONFIG
OE_N
VO/VPO
FSE0/VMO
RCV
VP
Level Translators
& Control Logic
Auto Connect &
Charger
Detection Control
HiZ &
Pull
Downs
+
-
CONFIG_INT
VREF
-
+
150k
+
-
VIO
VREG3V3
Vpu3V3
1.5k
(FS connection)
33 D+
D-
33
VM
HIZ
RHIZ
Figure 1. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FUSB1500 • Rev. 1.0.1
2
GND
www.fairchildsemi.com









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FUSB1501 Даташит, Описание, Даташиты
Pin Configuration
Figure 2. Pin Configuration (Top-Through View)
Pin Definitions
Pin # Name I/O
Description
1
OE_N
I
Output enable. Active LOW enables the transceiver to transmit data on the bus. When
not active, the transceiver is in the receive mode (CMOS level is relative to VIO).
Receive data output. Non-inverted CMOS level output for USB differential input (CMOS
2
RCV
O
output level is relative to VIO). Driven LOW when SUSPND mode is active; (SUSPND is
only enabled per the specific extended control table – see Table 4); RCV output is
stable and preserved during SE0 condition.
Single-ended D+ receiver output VP (CMOS level relative to VIO); used for external
3 VP O detection of SE0, error conditions, speed of connected device; driven HIGH when no
supply connected to VREG3V3.
Single-ended D- receiver output VM (CMOS level relative to VIO); used for external
4 VM O detection of SE0, error conditions, speed of connected device; driven HIGH when no
supply is connected to VREG3V3.
Suspend. Enables a low-power state (CMOS level is relative to VIO). While the
5 SUSPND I FUSB1500 is suspended, it drives the RCV pin to logic “0” state. (Suspend is only
enabled per the specific extended control table – see Table 4).
High-Z input (CMOS level is relative to VIO). HIGH selects the high-Z mode, which puts
6 HiZ I all the outputs, including VPU, in high impedance. There is a 100kweak pull-down on
this pin.
7 VIO
Supply voltage for digital I/O pins (1.65V to 3.6V). When not connected, the D+ and D-
pins are in three-state. This supply bus is independent of VPU and VREG3V3.
8
SPEED_N
I
Speed selection input (CMOS level relative to VIO); adjusts the slew rate of differential
outputs D+ and D- according to the extended control table (see Table 4).
9 D- AI/O Data- bus connection.
10 D+ AI/O Data+ bus connection; for FS peripheral mode, connect to VPU via 1.5k.
11
VO/VPO
I
Driver data input (CMOS level is relative to VIO); Schmitt-trigger input; VO is input pin
for SE Mode.
12
FSE0/VMO
I
Driver data input (CMOS level is relative to VIO); Schmitt-trigger input; FSE0 is input pin
for SE Mode, see Table 2 and Table 3.
13 VREG3V3
Supply voltage input for 3.3V operation.
This interrupt is active LOW. It is asserted when an SE0 is seen on the USB bus (SE0
14
INT_N
O detection circuit is only enabled per the specific extended control table). It is also
referenced to VIO.
Pull-up supply voltage (3.3V300mV); connect an external 1.5kresistor on D+
15 VPU
(FS data rate) or D- (LS data rate). Internal switch is controlled by the CONFIG,
SPEED_N, and SUSPND input pins (see Table 4).
16
CONFIG
I
USB connect or disconnect, software-control input. SPEED_N and SUSPND also gate
the pull-up resistor (see Table 4).
Exposed
Die Pad
GND
GND GND supply bonded to exposed die pad to be connected to the PCB GND.
© 2008 Fairchild Semiconductor Corporation
FUSB1500 • Rev. 1.0.1
3
www.fairchildsemi.com










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Номер в каталогеОписаниеПроизводители
FUSB1500USB2.0 Full-Speed / Low-Speed TransceiverFairchild Semiconductor
Fairchild Semiconductor
FUSB1501USB2.0 Full-Speed / Low-Speed TransceiverFairchild Semiconductor
Fairchild Semiconductor

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